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INTEGRATED CIRCUITS
DATA SHEET
SAA5X9X family Economy teletext and TV microcontrollers
Preliminary specification File under Integrated Circuits, IC02 1997 Jul 07
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.2 9.3 9.4 9.5 9.6 FEATURES General Microcontroller Teletext acquisition Teletext Display Additional features of SAA529xA devices Additional features of SAA549x devices GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Microcontroller 80C51 Features not supported Additional features Microcontroller interfacing TELETEXT DECODER Data slicer Acquisition timing Teletext acquisition Rolling headers and time Error checking Memory organisation of SAA5296/7, SAA5296/7A and SAA5496/7 Inventory page Memory Organisation of SAA5291, SAA5291A and SAA5491 Packet 26 processing VPS Wide Screen Signalling (SAA529xA and SAA549x only) 525-line world system teletext Fastext detection Page clearing Full channel operation Independent data services (SAA5291, SAA5291A, SAA5491 only) THE DISPLAY Introduction Character matrix East/West selection National option characters The twist attribute On Screen Display symbols 2 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 10 10.1 10.2 10.3 10.4 10.5 10.6 11 12 13 14 15 16 17 18 18.1 18.2 18.3 19 20 21
SAA5X9X family
Language group identification 525-line operation On Screen Display characters Control characters Quadruple width display (SAA549x) Page attributes Display modes On Screen Display boxes Screen colour Redefinable Colours (SAA549x) Cursor Other display features Display timing Horizontal timing Vertical timing Display position Clock generator CHARACTER SETS Pan-European Russian Greek/Turkish Arabic/English/French Thai Arabic/Hebrew LIMITING VALUES CHARACTERISTICS CHARACTERISTICS FOR THE I2C-BUS INTERFACE QUALITY SPECIFICATIONS APPLICATION INFORMATION EMC GUIDELINES PACKAGE OUTLINES SOLDERING Introduction SDIP QFP DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Jul 07
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
1 1.1 FEATURES General 1.4 Teletext Display
SAA5X9X family
* 525-line and 625-line display * 12 x 10 character matrix * Double height, width and size On-Screen Display (OSD) * Definable border colour * Enhanced display features including meshing and shadowing * 260 characters in mask programmed ROM * Automatic FRAME output control with manual override * RGB push pull output to standard decoder ICs * Stable display via slave synchronisation to Horizontal Sync and Vertical Sync. 1.5 Additional features of SAA529xA devices
* Single chip microcontroller with integrated teletext decoder * Single +5 V power supply * Single crystal oscillator for teletext decoder, display and microcontroller * Teletext function can be powered-down independently of microcontroller function for reduced power consumption in stand-by * Pin compatibility throughout family. 1.2 Microcontroller
* 80C51 microcontroller core * 16/32/64 kbyte mask programmed ROM * 256/768/1280 bytes of microcontroller RAM * Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals * One 14-bit PWM for Voltage Synthesis Tuner control * Four 8-bit Analog-to-Digital converters * 2 high current open-drain outputs for directly driving LED's etc. * I2C-bus interface * External ROM and RAM capability on QFP80 package version. 1.3 Teletext acquisition
* Wide Screen Signalling (WSS) bit decoding (line 23). 1.6 Additional features of SAA549x devices
* Wide Screen Signalling bit decoding (line 23) * Quad width OSD capability * 32 additional OSD characters in mask programmed ROM * 8 foreground and 8 background colours definable from a palette of 64. 2 GENERAL DESCRIPTION
* 1 page and 10 page Teletext version * Acquisition of 525-line and 625-line World System Teletext, with automatic selection * Acquisition and decoding of VPS data (PDC system A) * Page clearing in under 64 s (1 TV line) * Separate storage of extension packets (SAA5296/7, SAA5296/7A and SAA5496/7) * Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) (SAA5296/7, SAA5296/7A and SAA5496/7) * Automatic detection of FASTEXT transmission * Real-time packet 26 engine for processing accented (and other) characters * Comprehensive Teletext language coverage * Video signal quality detector.
The SAA529x, SAA529xA and SAA549x family of microcontrollers are a derivative of the Philips' industry-standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system and include an integrated teletext function. The teletext hardware has the capability of decoding and displaying both 525-line and 625-line World System Teletext. The same display hardware is used both for Teletext and On-Screen Display, which means that the display features give greater flexibility to differentiate the TV set. The family offers both 1 page and 10 page Teletext capability, in a range of ROM sizes. Increasing display capability is offered from the SAA5290 to the SAA5497.
1997 Jul 07
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
3 ORDERING INFORMATION TYPE NUMBER(1) NAME SAA5290PS/nnn SAA5291PS/nnn SAA5291APS/nnn SAA5296PS/nnn SAA5296APS/nnn SAA5491PS/nnn SAA5496PS/nnn SAA5291H/nnn SAA5291AH/nnn SAA5296H/nnn SAA5296AH/nnn SAA5491H/nnn SAA5496H/nnn SAA5297PS/nnn SAA5297APS/nnn SAA5497PS/nnn SAA5297H/nnn SAA5297AH/nnn SAA5497H/nnn Note QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) PACKAGE DESCRIPTION
SAA5X9X family
VERSION
PROGRAM MEMORY (ROM)
SDIP52 plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1 16 kbytes
SOT247-1 32 kbytes
SOT318-2 32 kbytes and external
SOT247-1 64 kbytes
SOT318-2 64 kbytes or external
1. `nnn' is a three-digit number uniquely referencing the microcontroller program mask and OSD mask. 4 QUICK REFERENCE DATA SYMBOL VDDA VDDM VDDT fxtal Tamb IDDM IDDA IDDT IDDA IDDT crystal frequency operating ambient temperature microcontroller supply current - -20 - - - - - 12 - 20 - +70 35 MHz C mA supply voltages PARAMETER MIN. 4.5 TYP. 5.0 MAX. 5.5 V UNIT
SAA5290, SAA5291, SAA5291A and SAA5491 analog supply current teletext supply current 35 40 50 65 mA mA
SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496 and SAA5497 analog supply current teletext supply current 35 50 50 80 mA mA
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
5 BLOCK DIAGRAM
SAA5X9X family
handbook, full pagewidth
BLACK
IREF
VDDA
VDDM VDDT
VSSA VSSD
CVBS0, CVBS1
DATA SLICER
TELETEXT ACQUISITION
DISPLAY
R, G, B, VDS, COR
ACQUISITION TIMING XTALIN XTALOUT OSCGND OSCILLATOR
PAGE RAM DISPLAY TIMING
SAA5X9X
512 x 8 AUX RAM 32K x 8 ROM 256 x 8 RAM TEXT INTERFACE
VSYNC HSYNC FRAME
data address 8051 MICROCONTROLLER int I2C-BUS INTERFACE TIMER/ CTRS ADC PWM
RESET
PORT 1
PORT 0
PORT 3
PORT 2
MGK462
P1.0 to P1.7
P0.0 to P0.7
P3.0 to P3.7
P2.0 to P2.7
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
6 6.1 PINNING INFORMATION Pinning
SAA5X9X family
handbook, halfpage
P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0
1 2 3 4 5 6 7 8 9
52
P1.5
51 P1.4 50 49 48 47 46 45 44 43 42 P1.7/SDA P1.6/SCL P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDM RESET XTALOUT
P3.1/ADC1 10 P3.2/ADC2 11 P3.3/ADC3 12 VSSD 13 P0.0 14 P0.1 15 P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 P0.7 VSSA CVBS0 CVBS1 BLACK IREF 20 21 22 23 24 25 26
MGK461
41 XTALIN 40 OSCGND
SAA5X9X
39 VDDT 38 VDDA 37 VSYNC 36 HSYNC 35 VDS 34 R 33 G 32 B 31 RGBREF 30 P3.4/PWM7 29 COR 28 VSSD
27 FRAME
Fig.2 Pin configuration (SDIP52).
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
77 P2.0/TPWM
80 P2.3/PWM2
79 P2.2/PWM1
78 P2.1/PWM0
66 P1.7/SDA
handbook, full pagewidth
65 P1.6/SCL 64 P1.1/T0 63 P1.0/INT1 62 VDDM 61 P1.3/T1 60 P1.2/INT0 59 RESET 58 XTALOUT 57 XTALIN 56 OSCGND 55 A8 54 A9 53 A10 52 A11 51 VDDT 50 REF+ 49 VDDA 48 P3.6 47 VSYNC 46 P3.5 45 HSYNC 44 P3.4/PWM7 43 VDS 42 R 41 G B 40
MGL157
68 P1.5 VSSD 37
P2.6/PWM5 1 P2.7/PWM6 2 P3.0/ADC0 3 n.c. 4 P3.1/ADC1 5 P3.2/ADC2 6 P3.3/ADC3 7 P2.5/PWM4 8 P2.4/PWM3 9 RD 10 WR 11 VSSD 12 EA 13 P0.0 14 P0.1 15 P0.2 16 PSEN 17 ALE 18 REF- 19 P0.3 20 P0.4 21 P3.7 22 n.c. 23 P0.5 24 P0.6 25 P0.7 26 VSSA 27 CVBS0 28 CVBS1 29 BLACK 30 IREF 31 A15 32 A14 33 A13 34 A12 35 FRAME 36 COR 38 RGBREF 39
SAA5X9X
Fig.3 Pin configuration (QFP80).
1997 Jul 07
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67 P1.4
76 AD7
75 AD6
74 AD5
73 AD4
72 AD3
71 AD2
70 AD1
69 AD0
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
6.2 Pin description SDIP52 and QFP80 packages PIN SYMBOL SDIP52 P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7 P3.5 P3.6 P3.7 VSSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 BLACK IREF FRAME VSSD COR 1 2 3 4 5 6 7 8 9 10 11 12 30 - - - 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 QFP80 77 78 79 80 9 8 1 2 3 5 6 7 44 46 48 22 12 14 15 16 20 21 24 25 26 27 28 29 30 31 36 37 38 Analog ground. Digital ground. Port 0: 8-bit open-drain bidirectional port. DESCRIPTION
SAA5X9X family
Table 1
Port 2: 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM. P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.
Port 3: 8-bit open-drain bidirectional port with alternative functions. P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility. P3.4/PWM7 is the output for the 6-bit PWM7.
P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs.
Composite video inputs; a positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor. Video black level storage input: this pin should be connected to VSSA via a 100 nF capacitor. Reference current input for analog circuits, connected to VSSA via a 27 k resistor. De-interlace output synchronised with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits. Internally connected; this pin should be connected to digital ground. Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
PIN SYMBOL SDIP52 LRGBREF B G R VDS HSYNC VSYNC VDDA VDDT OSCGND XTALIN XTALOUT RESET 31 32 33 34 35 36 37 38 39 40 41 42 43 QFP80 39 40 41 42 43 45 47 49 51 56 57 58 59 DC input voltage to define the output HIGH level on the RGB pins. Pixel rate output of the BLUE colour information. Pixel rate output of the GREEN colour information. Pixel rate output of the RED colour information. Video/data switch push-pull output for dot rate fast blanking. Schmitt trigger input for a TTL level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit TXT1.H POLARITY. Schmitt trigger input for a TTL level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit TXT1.V POLARITY. +5 V analog power supply. +5 V teletext power supply. Crystal oscillator ground. 12 MHz crystal oscillator input. 12 MHz crystal oscillator output. If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods) while the oscillator is running, the device is reset; this pin should be connected to VDDM via a 2.2 F capacitor. +5 V microcontroller power supply. Port 1: 8-bit open-drain bidirectional port with alternate functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. P1.1/T0 is the counter/timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the counter/timer 1. P1.6/SCL is the serial clock input for the I2C-bus. P1.7/SDA is the serial data port for the I2C-bus. REF+ REF- RD WR PSEN ALE EA AD0 to AD7 A8 to A15 - - - - - - - - - 50 19 10 11 17 18 13 69 to 76 55 to 52, 35 to 32 Positive reference voltage for software driven ADC. Negative reference voltage for software driven ADC. Read control signal to external Data Memory. Write control signal to external Data Memory. Enable signal for external Program Memory. External latch enable signal; active HIGH. Control signal used to select external (LOW) or internal (HIGH) Program Memory. Address lines A0 to A7 multiplexed with data lines D0 to D7. Address lines A8 to A15. DESCRIPTION
VDDM P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/INT1 P1.6/SCL P1.7/SDA P1.4 P1.5
44 45 46 47 48 49 50 51 52
62 63 64 60 61 65 66 67 68
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
7 7.1 FUNCTIONAL DESCRIPTION Microcontroller 7.3 Additional features
SAA5X9X family
The functionality of the microcontroller used in this family is described here with reference to the industry-standard 80C51 microcontroller. A full description of its functionality can be found in the "80C51-Based 8-Bit Microcontrollers; Data Handbook IC20". Using the 80C51 as a reference, the changes made to this family fall into two categories: * Features not supported by the SAA529x, SAA529xA or SAA549x devices * Features found on the SAA529x, SAA529xA or SAA549x devices but not supported by the 80C51. 7.2 7.2.1 80C51 features not supported INTERRUPT PRIORITY
The following features are provided in addition to the standard 80C51 features. 7.3.1 INTERRUPTS
The external INT1 interrupt is modified to generate an interrupt on both the rising and falling edges of the INT1 pin, when EX1 bit is set. This facility allows for software pulse width measurement for handling of a remote control. 7.3.2 BIT LEVEL I2C-BUS INTERFACE
The IP SFR is not implemented and all interrupts are treated with the same priority level. The normal prioritisation of interrupts is maintained within the level. Table 2 Interrupts and vectors address VECTOR ADDRESS 000H 003H 00BH 013H 01BH 02BH 053H note 1
For reasons of compatibility with SAA5290, the SAA5291, SAA5291A and SAA5491 contain a bit level serial I/O which supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification "The I2C-bus and how to use it (including specifications)" concerning the input levels and output drive capability. Consequently, these two pins have an open-drain output configuration. All the four following modes of the I2C-bus are supported. * Master transmitter * Master receiver * Slave transmitter * Slave receiver. Three SFRs support the function of the bit-level I2C-bus hardware: S1INT, S1BIT and S1SCS and are enabled by setting register bit TXT8.I2C SELECT to logic 0. 7.3.3 BYTE LEVEL I2C-BUS INTERFACE
INTERRUPT SOURCE Reset External INT0 Timer 0 External INT1 Timer 1 Byte I2C-bus Bit I2C-bus;
Note 1. SAA5290, SAA5291, SAA5291A and SAA5491 only. 7.2.2 OFF-CHIP MEMORY
The byte level serial I/O supports the I2C-bus protocol. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability. Consequently, these two pins have an open-drain output configuration. The byte level I2C-bus serial port is identical to the I2C-bus serial port on the 8xC552. The operation of the subsystem is described in detail in the 8xC552 data sheet found in "80C51-Based 8-Bit Microcontrollers; Data Handbook IC20". Four SFRs support the function of the byte level I2C-bus hardware, they are S1CON, S1STA, S1DAT and S1ADR and are enabled by setting register bit TXT8.I2C SELECT to logic 1. 7.3.4 LED SUPPORT
The SDIP52 version does not support the use of off-chip program memory or off-chip data memory. 7.2.3 IDLE AND POWER-DOWN MODES
As Idle and Power-down modes are not supported, their respective bits in PCON are not available. 7.2.4 UART FUNCTION
The 80C51 UART is not available. As a consequence the SCON and SBUF SFRs are removed and the ES bit in the IE SFR is unavailable.
Port pins P0.5 and P0.6 have a 10 mA current sinking capability to enable LEDs to be driven directly. 10
1997 Jul 07
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
7.3.5 6-BIT PWM DACS
SAA5X9X family
Eight 6-bit DACs are available to allow direct control of analog parts of the television. Each low resolution 6-bit DAC is controlled by its associated Special Function Register (PWM0 to PWM7). The PWM outputs are alternative functions of Port 2 and Port 3.4. The PWE bit in the SFR for the port corresponding to the PWM should be set to logic 1 for correct operation of the PWM, e.g. if PWM0 is to be used, P2.1 should be set to logic 1 setting the port pin to high-impedance.
7.3.5.1
Table 3 7 PWE Table 4 BIT 7
Pulse Width Modulator Registers (PWM0 to PWM7)
Pulse Width Modulator Registers (see Table 10 for addresses) 6 - 5 PV5 4 PV4 3 PV3 2 PV2 1 PV1 0 PV0
Description of PWMn bits (n = 0 to 7) SYMBOL PWE DESCRIPTION If PWE is set to a logic 1, the corresponding PWM is active and controls its assigned port pin. If PWE is set to a logic 0, the port pin is controlled by the corresponding bit in the port SFR. Not used. The output of the PWM is a pulse of period 21.33 s with a pulse HIGH time determined by the binary value of these 6-bits multiplied by 0.33 s. PV5 is the most significant bit.
6 5 4 3 2 1 0
- PV5 PV4 PV3 PV2 PV1 PV0
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
7.3.6 14-BIT PWM DAC
SAA5X9X family
One 14-bit DAC is available to allow direct control of analog sections of the television. The 14-bit PWM is controlled using Special Function Registers TDACL and TDACH. The output of the TPWM is a pulse of period 42.66 s. The 7 most significant bits, TDACH.TD13 (MSB) to TDACH.TD8 and TDACL.TD7, alter the pulse width between 0 and 42.33 s, in much the same way as
in the 6-bit PWMs. The 7 least significant bits, TDACL.TD6 to TDACL.TD0 (LSB), extend certain pulses by a further 0.33 s, e.g. if the 7 least significant bits are given the value 01H, then 1 in 128 cycles is extended. If the 7 least significant bits are given the value 02H, then 2 in 128 cycles is extended, and so forth. The TPWM will not start to output a new value until after writing a value to TDACH. Therefore, if the value is to be changed, TDACL should be written to before TDACH.
7.3.6.1
Table 5 7 PWE Table 6 BIT 7 6 5 4 3 2 1 0
TPWM High Byte Register (TDACH)
TPWM High Byte Register (SFR address D3H) 6 - 5 TD13 4 TD12 3 TD11 2 TD10 1 TD9 0 TD8
Description of TDACH bits SYMBOL PWE - TD13 TD12 TD11 TD10 TD9 TD8 DESCRIPTION If PWE is set to a logic 1, the TPWM is active and controls port line P2.0. If PWE is set to a logic 0, the port pin is controlled by the corresponding bit in the port SFR. Not used. These 6-bits along with bit TD7 in the TDACL register control the pulse width period. TD13 is the most significant bit.
7.3.6.2
Table 7 7 TD7 Table 8 BIT 7 6 to 0
TPWM Low Byte Register (TDACL)
TPWM Low Byte Register (SFR address D2H) 6 TD6 5 TD5 4 TD4 3 TD3 2 TD2 1 TD1 0 TD0
Description of TDACL bits SYMBOL TD7 TD6 to TD0 DESCRIPTION This bit is used with bits TD13 to TD8 in the TDACH register to control the pulse width period. These 7-bits extend certain pulses by a further 0.33 s.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
7.3.7 SOFTWARE ADC
SAA5X9X family
Up to 4 successive approximation ADCs can be implemented in software by making use of the on-chip 8-bit DAC and multiplexed voltage comparator. The software ADC uses 4 analog inputs which are multiplexed with P3.0 to P3.3. Table 9 ADC input channel selection CH0 0 1 0 1 INPUT PIN P3.3/ADC3 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2
must be performed at least 1 instruction cycle before the setting of SAD.ST to ensure comparison is made using the correct SAD.SAD7 to SAD.SAD4 value. The output of the comparator is SAD.VHI, and is valid after 1 instruction cycle following the setting of SAD.ST to a logic 1.
CH1 0 0 1 1
handbook, halfpage
P3.0 P3.1
ST
C1 1D VH1
MULTIPLEXER P3.2 P3.3 8-BIT DAC CH1, CH0 REF- REF+
The control of the ADC is achieved using the Special Function Registers SAD and SADB. SAD.CH1 and SAD.CH0 select one of the four inputs to pass to the comparator. The other comparator input comes from the DAC, whose value is set by SAD.SAD7 (MSB) to SAD.SAD4 and SADB.SAD3 to SADB.SAD0 (LSB). The setting of the value SAD.SAD7 to SAD.SAD4
SAD7 to SAD0
MGL115
Fig.4 SAD block diagram.
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Philips Semiconductors
7.4
Microcontroller interfacing
Economy teletext and TV microcontrollers
The 80C51 communicates with the peripheral functions using Special Function Registers (SFRs) which are addressed as RAM locations. The registers in the teletext decoder appear as normal SFRs in the microcontroller memory map, but are written to using an internal serial bus. The SFR map is given in Table 10. 7.4.1 SPECIAL FUNCTION REGISTER MAP
Table 10 Special Function Register map; note 1 SYMBOL
ACC(2) B(2) DPTR
NAME
Accumulator B register Data Pointer (2 bytes)
DIRECT ADDR. (HEX)
E0 F0
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7
E7 - F7 -
6
E6 - F6 -
5
E5 - F5 -
4
E4 - F4 -
3
E3 - F3 -
2
E2 - F2 -
1
E1 - F1 -
0
E0 - F0 -
RESET VALUE (HEX)
00 00
DPH DPL
IE(2)(3) P0(2) P1(2) P2(2) P3(2)(3) PCON(3)
High byte Low byte
Interrupt Enable Port 0 Port 1 Port 2 Port 3 Power Control
83 82 A8 80 90 A0 B0 87
- - AF EA 87 - 97 - A7 - B7 - -
- - AE ES1 86 - 96 - A6 - B6 - ARD
- - AD ES2 85 - 95 - A5 - B5 - -
- - AC * 84 - 94 - A4 - B4 - *
- - AB ET1 83 - 93 - A3 - B3 - GF1
- - AA EX1 82 - 92 - A2 - B2 - GF0
- - A9 ET0 81 - 91 - A1 - B1 - -
- - A8 EX0 80 - 90 - A0 - B0 - -
00 00 00 FF FF FF FF
SAA5X9X family
Preliminary specification
10
1997 Jul 07 15
Philips Semiconductors
SYMBOL
PSW(2) PWM0(3) PWM1(3) PWM2(3) PWM3(3) PWM4(3) PWM5(3) PWM6(3) PWM7(3) S1ADR(3) S1CON
(2)(3)(4)
NAME
Program Status Word Pulse Width Modulator 0 Pulse Width Modulator 1 Pulse Width Modulator 2 Pulse Width Modulator 3 Pulse Width Modulator 4 Pulse Width Modulator 5 Pulse Width Modulator 6 Pulse Width Modulator 7 Serial I2C-bus address Serial I2C-bus control Serial I2C-bus control Serial I2C-bus data Serial I2C-bus Interrupt
DIRECT ADDR. (HEX)
D0 D5 D6 D7 DC DD DE DF D4 DB D8 D8 DA DA
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7
D7 CY PWE PWE PWE PWE PWE PWE PWE PWE ADR6 DF CR2 DF SDI DAT7 SI
6
D6 AC * * * * * * * * ADR5 DE ENSI DE SCI DAT6 -
5
D5 F0 PV5 PV5 PV5 PV5 PV5 PV5 PV5 PV5 ADR4 DD STA DD CLH DAT5 -
4
D4 RS1 PV4 PV4 PV4 PV4 PV4 PV4 PV4 PV4 ADR3 DC STO DC BB DAT4 -
3
D3 RS0 PV3 PV3 PV3 PV3 PV3 PV3 PV3 PV3 ADR2 DB SI DB RBF DAT3 -
2
D2 OV PV2 PV2 PV2 PV2 PV2 PV2 PV2 PV2 ADR1 DA AA DA WBF DAT2 -
1
D1 * PV1 PV1 PV1 PV1 PV1 PV1 PV1 PV1 ADR0 D9 CR1 D9 STR DAT1 -
0
D0 P PV0 PV0 PV0 PV0 PV0 PV0 PV0 PV0 GC D8 CR0 D8 ENS DAT0 -
RESET VALUE (HEX)
00 40 40 40 40 40 40 40 40 00
Economy teletext and TV microcontrollers
00 E0 00
S1SCS
(2)(3)(5)
S1DAT
(3)(4)
SAA5X9X family
S1INT
(3)(5)
7F
Preliminary specification
1997 Jul 07 16
Philips Semiconductors
SYMBOL
S1STA
(3)(4)
NAME
Serial I2C-bus status Serial I2C-bus data Software ADC (MSB) Software ADC (LSB) Stack Pointer
DIRECT ADDR. (HEX)
D9 D9 E8 98 81 88 D3 D2 8C 8D 8A 8B 89 C0
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7
STAT4 SDO/SDI EF VHI 9F - 8F TF1 PWE TD7 TH07 TH17 TL07 TL17 GATE X24 POSN
6
STAT3 - EE CH1 9E - 8E TR1 * TD6 TH06 TH16 TL06 TL16 C/T Timer 1 DISPLAY X24
5
STAT2 - ED CH0 9D - 8D TF0 TD13 TD5 TH05 TH15 TL05 TL15 M1 AUTO FRAME
4
STAT1 - EC ST 9C - 8C TR0 TD12 TD4 TH04 TH14 TL04 TL14 M0 DISABLE HDR ROLL X26 OFF
3
STAT0 - EB SAD7 9B SAD3 8B IE1 TD11 TD3 TH03 TH13 TL03 TL13 GATE DISPLAY STATUS ROW ONLY FULL FIELD
2
0 - EA SAD6 9A SAD2 8A IT1 TD10 TD2 TH02 TH12 TL02 TL12 C/T Timer 0 DISABLE FRAME
1
0 - E9 SAD5 99 SAD1 89 IE0 TD9 TD1 TH01 TH11 TL01 TL11 M1 VPS ON
0
0 - E8 SAD4 98 SAD0 88 IT0 TD8 TD0 TH00 TH10 TL00 TL10 M0 INV ON
RESET VALUE (HEX)
F8 7F 00 00 07 00 40 00 00 00 00 00 00 00
Economy teletext and TV microcontrollers
S1BIT
(3)(5)
SAD
(2)(3)
SADB
(2)(3)
SP TCON(2) TDACH TDACL TH0 TH1 TL0 TL1 TMOD TXT0(3)
Timer/counter control TPWM High byte
TPWM Low byte Timer 0 High byte Timer 1 High byte Timer 0 Low byte Timer 1 Low byte Timer/counter mode Teletext Register 0
SAA5X9X family
Preliminary specification
TXT1(3)
Teletext Register 1
C1
EXT PKT OFF
8-BIT
ACQ OFF
FIELD H V POLARITY POLARITY POLARITY
00
1997 Jul 07 17
Philips Semiconductors
SYMBOL
TXT2(3) TXT3(3) TXT4(3)
NAME
Teletext Register 2 Teletext Register 3 Teletext Register 4 Teletext Register 5 Teletext Register 6 Teletext Register 7 Teletext Register 8 Teletext Register 9 Teletext Register 10 Teletext Register 11 Teletext Register 12 Teletext Register 13
DIRECT ADDR. (HEX)
C2 C3 C4
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7
* * OSD BANK ENABLE BKGND OUT BKGND OUT STATUS ROW TOP I2C SELECT CURSOR FREEZE * D7 625/525 SYNC BF VPS RECEIVE D
6
REQ3 * QUAD WIDTH ENABLE
5
REQ2 * EAST/ WEST
4
REQ1 PRD4 DISABLE DBL HT COR IN COR IN TOP/ BOTTOM DISABLE SPANISH R4 C4 D4 ROM VER R2 BC 525 TEXT
3
REQ0 PRD3 B MESH ENABLE TEXT OUT TEXT OUT DOUBLE HEIGHT PKT26 RECEIVE D R3 C3 D3 ROM VER R1 BB 625 TEXT PAGE3
2
SC2 PRD2 C MESH ENABLE TEXT IN TEXT IN BOX ON 24 WSS RECEIVE D R2 C2 D2 ROM VER R0 BA PKT 8/30 PAGE2
1
SC1 PRD1 TRANS ENABLE PICTURE ON OUT PICTURE ON OUT BOX ON 1-23 WSS ON
0
SC0 PRD0 SHADOW ENABLE PICTURE ON IN PICTURE ON IN BOX ON 0 CVBS0/ CVBS1 R0 C0 D0 VIDEO SIGNAL QUALITY B8 TIB
RESET VALUE (HEX)
00 00 00
Economy teletext and TV microcontrollers
TXT5(3) TXT6(3) TXT7(3) TXT8(3)
C5 C6 C7 C8
BKGND IN COR OUT BKGND IN COR OUT CURSOR ON IDS ENABLE CLEAR MEMORY. * D6 ROM VER R4 BE PAGE CLEARIN G - REVEAL *
03 03 00 00
TXT9(3) TXT10(3) TXT11(3) TXT12(3)
C9 CA CB CC
A0 C5 D5 ROM VER R3 BD 525 DISPLAY
R1 C1 D1 TXT ON
00 00 00 0XXXX X00B 00
TXT13
(2)(3)
B8
B9 FASTEXT
SAA5X9X family
Preliminary specification
TXT14(3)
Teletext Register 14
CD
-
-
PAGE1
PAGE0
00
1997 Jul 07 18
Philips Semiconductors
SYMBOL
TXT15(3) TXT16(3) TXT17(3) WSS1(3)
NAME
Teletext Register 15 Teletext Register 16 Teletext Register 17 WSS Register 1 WSS Register 2 WSS Register 3 CLUT Register
DIRECT ADDR. (HEX)
CE CF B9 BA
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7
- - - -
6
- Y2 FORCE ACQ 1 -
5
- Y1 FORCE ACQ 0 -
4
- Y0 FORCE 625 WSS0 to WSS3 ERROR WSS4 to WSS7 ERROR WSS11
3
BLOCK3 - FORCE 525 WSS3
2
BLOCK2 - SCREEN COL2 WSS2
1
BLOCK1 X1 SCREEN COL1 WSS1
0
BLOCK0 X0 SCREEN COL0 WSS0
RESET VALUE (HEX)
00 00 00 00
Economy teletext and TV microcontrollers
WSS2(3)
BB
-
-
-
WSS7
WSS6
WSS5
WSS4
00
WSS3(3)
BC
WSS11 to WSS13 ERROR CLUT ENABLE
WSS13
WSS12
WSS8 to WSS10 ERROR G1 or ENTRY 3
WSS10
WSS9
WSS8
00
CLUT(3)
BD
CLUT ADDRESS
B1 or -
B0 or -
G0 or ENTRY 2
R1 or ENTRY 1
R0 or ENTRY 0
00
Notes 1. The asterisk (*) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. SFRs are bit addressable. 3. SFRs are modified or added to the 80C51 SFRs. 4. This register used for Byte Orientated I2C-bus, TXT8.I2C SELECT = 1. 5. This register used for Bit Orientated I2C-bus, TXT8.I2C SELECT = 0.
SAA5X9X family
Preliminary specification
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
7.4.2 SPECIAL FUNCTION REGISTERS BIT DESCRIPTIONS
SAA5X9X family
Table 11 SFRs bit description REGISTER Interrupt Enable Register (IE) EA ES1 ES2 ET1 EX1 ET0 EX0 disable all interrupts (logic 0) or use individual interrupt enable bits (logic 1) bit I2C-bus interrupt enable (logic 1) byte I2C-bus interrupt enable (logic 1) enable timer 1 overflow interrupt (logic 1) enable external interrupt 1 (logic 1) enable timer 0 overflow interrupt (logic 1) enable external interrupt 0 (logic 1) FUNCTION
Power Control Register (PCON) ARD GF1 GF0 AUX-RAM disable bit. Disables the 512 bytes of internal AUX-RAM (logic 1); all MOVX-instructions access the external data memory general purpose flag 1 general purpose flag 0
Program Status Word (PSW) CY AC F0 RS1,RS0 OV P carry flag auxiliary carry flag flag 0 register bank select control bits overflow flag parity flag
6-bit Pulse Width Modulator Control Registers (PWM0 to PWM7) PWE PV5 to PV0 activate this PWM and take control of respective port pin (logic 1) binary value sets high time of PWM output I2C-bus slave address to which the device will respond enables response to the I2C-bus general call address
Serial Interface Slave Address Register (S1ADR); note 1 ADR6 to ADR0 GC
Serial Interface Control Register (S1CON); note 1 CR2 to CR0 ENSI STA STO SI AA clock rate bits I2C-bus interface enable start condition flag stop condition flag interrupt flag assert acknowledge flag
1997 Jul 07
19
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
REGISTER Serial Interface Data Register (S1DAT); note 1 DAT7 to DAT0 I2C-bus data
FUNCTION
Serial Interface Status Register (S1STA) - READ only; note 1 STAT4 to STAT0 I2C-bus interface status
Serial Interface Data Register (S1BIT) - READ; note 2 SDI I2C-bus data bit input I2C-bus data bit output I2C-bus interrupt flag
Serial Interface Data Register (S1BIT) - WRITE; note 2 SDO
Serial Interface Interrupt Register (S1INT); note 2 SI
Serial Interface Control Register (S1SCS) - READ; note 2 SDI SCI CLH BB RBF WBF STR ENS serial data input at SDA serial clock input at SCL clock LOW-to-HIGH transition flag bus busy flag read bit finished flag write bit finished flag clock stretching enable (logic 1) enable serial I/O (logic 1)
Serial Interface Control Register (S1SCS) - WRITE; note 2 SDO SCO CLH STR ENS serial data output at SDA serial clock output at SCL clock LOW-to-HIGH transition flag clock stretching enable (logic 1) enable serial I/O (logic 1)
Software ADC Control Register (SAD) VHI CH1 and CH0 ST SAD7 to SAD4 comparator output indicating that analog input voltage greater than DAC voltage (logic 1) ADC input channel selection bits; see Table 11 initiate voltage comparison (logic 1); this bit is automatically reset to logic 0 4 MSB's of DAC input value
1997 Jul 07
20
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
REGISTER Software ADC Control Register (SADB) SAD3 to SAD0 4 LSB's of DAC input value
FUNCTION
Timer/Counter Control Register (TCON) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 timer 1 overflow flag timer 1 run control bit timer 0 overflow flag timer 0 run control bit interrupt 1 edge flag interrupt 1 type control bit interrupt 0 edge flag interrupt 0 type control bit
14-bit PWM MSB Register (TDACH) PWE TD13 to TD8 activate this 14-bit PWM and take over port pin (logic 1) 6 MSBs of 14-bit number to be output by the 14-bit PWM
14-bit PWM LSB Register (TDACL) TD7 to TD0 8 LSBs of 14-bit number to be output by the 14-bit PWM
Timer 0 High byte (TH0) TH07 to TH00 8 MSBs of Timer 0 16-bit counter
Timer 1 High byte (TH1) TH17 to TH10 8 MSBs of Timer 1 16-bit counter
Timer 0 Low byte (TL0) TL07 to TL00 8 LSBs of Timer 0 16-bit counter
Timer 1 Low byte (TL1) TL17 to TL10 8 LSBs of Timer 1 16-bit counter
Timer/Counter Mode Control Register (TMOD) GATE C/T M1, M0 gating control counter or timer selector mode control bits
1997 Jul 07
21
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
REGISTER Teletext Register 0 (TXT0) - WRITE only X24 POSN DISPLAY X24 AUTO FRAME DISABLE HDR ROLL DISPLAY STATUS ROW ONLY DISABLE FRAME VPS ON INV ON(3) EXT PKT OFF(3) 8-BIT ACQ OFF X26 OFF FULL FIELD FIELD POLARITY H POLARITY V POLARITY REQ3 to REQ0(3) SC2 to SC0
FUNCTION
store packet 24 in extension packet memory (logic 0) or page memory (logic 1) display X24 from page memory (logic 0) or extension packet memory (logic 1) FRAME output switched off automatically if any video displayed (logic 1) disable writing of rolling headers and time into memory (logic 1) display row 24 only (logic 1) FRAME output always LOW (logic 1) enable capture of VPS data (logic 1) enable capture of inventory page in block 8 (logic 1)
Teletext Register 1 (TXT1) - WRITE only disable decoding of extension packets (logic 1) data in packets 0 to 24 written into memory without error checking (logic 1) prevent teletext acquisition section writing to memory (logic 1) disable automatic processing of packet 26 data (logic 1) decode teletext on VBI lines only (logic 0) or decode teletext on any line (logic 1) VSYNC in first half of the line (logic 0) or second half of the line (logic 1) at start of even field HSYNC input positive-going (logic 0) or negative-going (logic 1) VSYNC input positive-going (logic 0) or negative-going (logic 1)
Teletext Register 2 (TXT2) - WRITE only selects which page is modified by TXT3 page request data start column at which page request data written to TXT3, page request data is placed
Teletext Register 3 (TXT3) - WRITE only PRD4 to PRD0 page request data
Teletext Register 4 (TXT4) - WRITE only OSD BANK ENABLE(4) QUAD WIDTH ENABLE(4) EAST/ WEST DISABLE DBL HGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE bank switching of OSD enabled (logic 1) enable quad width characters (logic 1) western languages selected (logic 0) or Eastern languages selected (logic 1) disable display of double height teletext control codes (logic 1) in OSD boxes enable meshing of area with black background (logic 1) enable meshing of area with other background colours (logic 1) set black background to transparent i.e. video is displayed (logic 1) enable south-east shadowing (logic 1)
1997 Jul 07
22
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
REGISTER Teletext Register 5 (TXT5) - WRITE only BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN
FUNCTION
background colour displayed outside teletext boxes (logic 1) background colour displayed inside teletext boxes (logic 1) COR output active outside teletext boxes (logic 1) COR output active inside teletext boxes (logic 1) text displayed outside teletext boxes (logic 1) text displayed inside teletext boxes (logic 1) video picture displayed outside teletext boxes (logic 1) video picture displayed inside teletext boxes (logic 1)
Teletext Register 6 (TXT6) - WRITE only See TXT5 this register has the same meaning as TXT5 but is only invoked if either newsflash (C5) or subtitle (C6) bit in row 25 of the basic page memory is set
Teletext Register 7 (TXT7) - WRITE only STATUS ROW TOP CURSOR ON REVEAL TOP/BOTTOM DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 I2C SELECT(2) IDS ENABLE(2) DISABLE SPANISH(2) PKT 26 RECEIVED WSS WSS RECEIVED(5) ON(5) display row 24 below (logic 0) or above (logic 1) teletext page display cursor at location pointed to by TXT9 and TXT10 (logic 1) display characters in areas with the conceal attribute set (logic 1) display rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set display each character as twice normal height (logic 1) enable teletext boxes in memory row 24 (logic 1) enable teletext boxes in memory rows 1 to 23 (logic 1) enable teletext boxes in memory row 0 (logic 1) select bit I2C-bus (logic 0) or byte I2C-bus (logic 1) capture teletext Independent Date Services (logic 1) disable special treatment of Spanish packet 26 decoding set to logic 1 when packet 26 teletext data processed set to logic 1 when wide screen signalling data received enable acquisition of wide screen signalling data select CVBS0 (logic 0) or CVBS1 (logic 1) input to the device
Teletext Register 8 (TXT8)
CVBS0/CVBS1
Teletext Register 9 (TXT9) - WRITE only CURSOR FREEZE CLEAR MEMORY A0 R4 to R0 locks current cursor position (logic 1) write 20H into every location in teletext memory (logic 1) TXT11 accesses the basic page memory, selected by TXT15 on the 10 page device, (logic 0) or extension packet memory (logic 1) memory row to be accessed by TXT11
1997 Jul 07
23
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
REGISTER Teletext Register 10 (TXT10) - WRITE only C5 to C0
FUNCTION
memory column to be accessed by TXT11
Teletext Register 11 (TXT11) D7 to D0 data byte written to, or read from teletext memory
Teletext Register 12 (TXT12) - READ only 625/525 SYNC ROM VER R4 to R0 TXT ON VIDEO SIGNAL QUALITY a 625-line CVBS signal (logic 0), or a 525-line CVBS signal (logic 1) is being input mask programmable identification for character set power has been applied to the teletext hardware (logic 1) CVBS input can be locked on by the teletext decoder (logic 1)
Teletext Register 13 (TXT13) VPS RECEIVED PAGE CLEARING 525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT TIB set to logic 1 when VPS data is received set when software requested page clear in progress set to logic 1 when 525-line syncs are driving the display set to logic 1 when 525-line teletext is received set to logic 1 when 625-line teletext is received set to logic 1 when packet 8/30 is detected set to logic 1 when packet X27/0 is detected text interface busy; logic 1 indicates that TXT registers 0 to 16 cannot currently be accessed
Teletext Register 14 (TXT 14) - WRITE only; note 3 PAGE3 to PAGE0 selects which page to display
Teletext Register 15 (TXT15) - WRITE only; note 3 BLOCK3 to BLOCK0 selects which memory block accessed by TXT9, 10 and 11 Teletext Register 16 (TXT16) - WRITE only Y2 to Y0 X1 to X0 sets vertical position of display area sets horizontal position of display area
Teletext Register 17 (TXT17) - Write only FORCE ACQ0,1 FORCE 625 FORCE 525 force acquisition mode force display to 625-line mode force display to 525-line mode
SCREEN COL 2 to 0 defines colour displayed instead of TV picture and black background
1997 Jul 07
24
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
REGISTER
FUNCTION
Wide Screen Signalling Register 1 (WSS1) - READ only; note 5 WSS 0-3 ERROR WSS3 to WSS0 error flag for bits WSS0 to WSS3 signalling bits to define aspect ratio (group 1)
Wide Screen Signalling Register 2 (WSS2) - READ only; note 5 WSS 4-7 ERROR WSS7 to WSS4 error flag for bits WSS4 to WSS7 signalling bits to define enhanced services (group 2)
Wide Screen Signalling Register 3 (WSS3) - READ only; note 5 WSS11-13 ERROR WSS13 to WSS11 WSS8-10 ERROR WSS10 to WSS8 error flag for bits WSS11 to WSS13 signalling bits to define reserved elements (group 4) error flag for bits WSS8 to WSS10 signalling bits to define subtitles (group 3)
Colour Look-Up Table Register (CLUT) - WRITE only; note 4 CLUT ENABLE CLUT ADDRESS B1 B0 G1 or ENTRY3 G0 or ENTRY2 R1 or ENTRY1 R0 or ENTRY0 Notes 1. Available on SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496, SAA5497 permanently and SAA5290, SAA5291, SAA5291A, SAA5491 when TXT8.I2C SELECT set to logic 1. 2. Available on SAA5290, SAA5291, SAA5291A and SAA5491. 3. Available on SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496, SAA5497. 4. Available on SAA5491, SAA5496, SAA5497. 5. Available on SAA5291A, SAA5296A, SAA5297A, SAA5491, SAA5496, SAA5497. enable the colour look-up table (logic 1) load CLUT address (logic 1) or CLUT data (logic 0) most significant BLUE component data least significant BLUE component data most significant GREEN component data or most significant bit of CLUT address least significant GREEN component data or CLUT address most significant RED component data or CLUT address least significant RED component data or least significant bit of CLUT address
1997 Jul 07
25
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8 8.1 TELETEXT DECODER Data slicer
SAA5X9X family
The data slicer extracts the digital teletext data from the incoming analog waveform. This is performed by sampling the CVBS waveform and processing the samples to extract the teletext data and clock. 8.2 Acquisition timing
The acquisition timing is generated from a logic level positive-going composite sync signal VCS. This signal is generated by a sync separator circuit which adaptively slices the sync pulses. The acquisition clocking and timing are locked to the VCS signal using a digital phase-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected. 8.3 Teletext acquisition
When the HOLD bit is set to a logic 0 the teletext decoder will not recognise any page as having the correct page number and no pages will be captured. In addition to providing the user requested hold function this bit should be used to prevent the inadvertent capture of an unwanted page when a new page request is being made. For example, if the previous page request was for page 100 and this was being changed to page 234, it would be possible to capture page 200 if this arrived after only the requested magazine number had been changed. The E1 and E0 bits control the error checking which should be carried out on packets 1 to 23 when the page being requested is captured. This is described in more detail in Section 8.5. For the ten page device, each packet can only be written into one place in the teletext RAM so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request. At power-up each page request defaults to any page, hold on and error check Mode 0. Table 12 The contents of the Page request RAM START COLUMN 0 1 2 3 PRD4 DO CARE Magazine DO CARE Page Tens PRD3 PRD2 PRD1 PRD0 HOLD MAG2 MAG1 MAG0 PT3 PT2 PU2 X PT1 PU1 HT1 PT0 PU0 HT0
This family is capable of acquiring 625-line and 525-line World System Teletext see "World System Teletext and Data Broadcasting System". Teletext pages are identified by seven numbers: magazine (page hundreds), page tens, page units, hours tens, hours units, minutes tens and minutes units. The last four digits, hours and minutes, are known as the subcode, and were originally intended to be time related, hence their names. A page is requested by writing a series of bytes into the TXT3 SFR which corresponds to the number of the page required. The bytes written into TXT3 are put into a small RAM with an auto-incrementing address. The start address for the RAM is set using the TXT2 SFR. Table 12 shows the contents of the page request RAM. TXT2.REQ0 to TXT2.REQ3 determine which of the 10 page requests is being modified for a 10 page teletext decoder. If TXT2.REQ is given a value greater than 09H, then data written into TXT3 is ignored. Up to 10 pages of teletext can be acquired on the 10 page device, when TXT1.EXT PKT OFF is set to logic 1, and up to 9 pages can be acquired when this bit is set to logic 0. If the `DO CARE' bit for part of the page number is set to a logic 0 then that part of the page number is ignored when the teletext decoder is deciding whether a page being received off air should be stored or not. For example, if the `DO CARE' bits for the 4 subcode digits are all set to logic 0s then every subcode version of the page will be captured.
DO CARE PU3 Page Units DO CARE Hours Tens DO CARE Hours Units DO CARE Minutes Tens DO CARE Minutes Units X X
4
HU3
HU2
HU1
HU0
5
X
MT2
MT1
MT0
6
MU3
MU2
MU1
MU0
7
X
X
E1
E0
1997 Jul 07
26
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
Table 13 Notation used in Table 12 MNEMONIC MAG PT PU HT HU MT MU E 8.4 DESCRIPTION Magazine Page Tens Page Units Hours Tens Hours Units Minutes Tens Minutes Units Error check mode
SAA5X9X family
The last 8 characters of the page header are used to provide a time display and are always extracted from every valid page header as it arrives and written into the display block. The TXT0.DISABLE HEADER ROLL bit prevents any data being written into row 0 of the page memory except when a page is acquired off air i.e. rolling headers and time are not written into the memory. The TXT1.ACQ OFF bit prevents any data being written into the memory by the teletext acquisition section. When a parallel magazine mode transmission is being received only headers in the magazine of the page requested are considered valid for the purposes of rolling headers and time. Only one magazine is used even if don't care magazine is requested. When a serial magazine mode transmission is being received all page headers are considered to be valid. 8.5 Error checking
Rolling headers and time
When a new page has been requested it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page has been found. When a page request is changed (i.e. when the TXT3 SFR is written to) a flag (PBLF) is written into bit 5, column 9, row 25 of the corresponding block of the page memory. The state of the flag for each block is updated every TV line, if it is set for the current display block, the acquisition section writes all valid page headers which arrive into the display block and automatically writes an alphanumeric green character into column 7 of row 0 of the display block every TV line. When a requested page header is acquired for the first time, rows 1 to 23 of the relevant memory block are cleared to space, i.e. have 20H written into every column, before the rest of the page arrives. Row 24 is also cleared if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF bit is set the extension packets corresponding to the page are also cleared.
Before teletext packets are written into the page memory they are error checked. The error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. If uncorrectable errors are detected in any other Hamming checked data the byte is not written into the memory.
1997 Jul 07
27
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
Packet X/0 handbook, full pagewidth '8-bit' bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/1-23 '8-bit' bit = 0, error check mode = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/24 '8-bit' bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/27/0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet 8/30/0,1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet 8/30/2,3,4-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
MGK465
8-bit data
odd parity checked
8/4 Hamming checked
Fig.5 Error checking.
1997 Jul 07
28
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8.6 Memory organisation of SAA5296/7, SAA5296/7A and SAA5496/7
SAA5X9X family
The teletext memory is divided into 10 blocks. Normally, when the TXT1.EXT PKT OFF bit is logic 0, each of blocks 0 to 8 contains a teletext page arranged in the same way as the basic page memory (see Fig.6) of the page device and block 9 contains extension packets (see Fig.7). When the TXT1.EXT PKT OFF bit is logic 1, no extension packets are captured and block 9 of the memory is used to store another page. The number of the memory block into which a page is written corresponds to the page request number which resulted in the capture of the page. Packet 0, the page header, is split into 2 parts when it is written into the text memory. The first 8 bytes of the header contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25 (see Table 15). Row 25 also contains the magazine number of the acquired page and the PBLF flag but the last 14 bytes are unused and may be used by the software, if necessary. The Hamming error flags are set if the on-board 8/4 Hamming checker detects that there has been an uncorrectable (2 bit) error in the associated byte. It is possible for the page to still be acquired if some of the page address information contains uncorrectable errors if that part of the page request was a `don't care'. There is no error flag for the magazine number as an uncorrectable error in this information prevents the page being acquired.
The interrupted sequence (C9) bit is automatically dealt with by the acquisition section so that rolling headers do not contain discontinuities in the page number sequence. The magazine serial (C11) bit indicates whether the transmission is a serial or a parallel magazine transmission. This affects the way the acquisition section operates and is dealt with automatically. The newsflash (C5), subtitle (C6), suppress header (C7), inhibit display (C10) and language control (C12 to 14) bits are dealt with automatically by the display section, described below. The update (C8) bit has no effect on the hardware. The remaining 32 bytes of the page header are parity checked and written into columns 8 to 39 of row 0. Bytes which pass the parity check have the MSB set to a logic 0 and are written into the page memory. Bytes with parity errors are not written into the memory. Table 14 Notation used in Table 15 MNEMONIC MAG PT PU HT HU MT MU DESCRIPTION Magazine Page Tens Page Units Hours Tens Hours Units Minutes Tens Minutes Units
Table 15 The data in row 25 of the basic page memory COL 0 1 2 3 4 5 6 7 8 9 10 to 23 BIT 7 0 0 0 0 0 0 0 0 0 0 - BIT 6 0 0 0 0 0 0 0 0 0 0 - BIT 5 0 0 0 0 0 0 0 0 0 PBLF - BIT 4 Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error FOUND 0 unused BIT 3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 - BIT 2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 - BIT 1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 - BIT 0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 -
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
handbook, full pagewidth
Basic Page Blocks (0 to 8/9) 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Control Data 9 6 7 8 Packet X/0 Packet X/1 Packet X/2 Packet X/3 Packet X/4 Packet X/5 Packet X/6 Packet X/7 Packet X/8 Packet X/9 Packet X/10 Packet X/11 Packet X/12 Packet X/13 Packet X/14 Packet X/15 Packet X/16 Packet X/17 Packet X/18 Packet X/19 Packet X/20 Packet X/21 Packet X/22 Packet X/23 Packet X/24(1) VPS Data(2) 23
MGK466
39
OSD only
(1) If `X24 Posn' bit = 1. (2) VPS data block 9, unused in blocks 0 to 8.
Fig.6 Packet storage locations.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
Extension Packet Block (9)
handbook, full pagewidth
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 9
Packet X/24 for page in block 0(1) Packet X/27/0 for page in block 0 Packet 8/30/0.1 Packet 8/30/2.3 Packet X/24 for page in block 1(1) Packet X/27/0 for page in block 1 Packet X/24 for page in block 2(1) Packet X/27/0 for page in block 2 Packet X/24 for page in block 3(1) Packet X/27/0 for page in block 3 Packet X/24 for page in block 4(1) Packet X/27/0 for page in block 4 Packet X/24 for page in block 5(1) Packet X/27/0 for page in block 5 Packet X/24 for page in block 6(1) Packet X/27/0 for page in block 6 Packet X/24 for page in block 7(1) Packet X/27/0 for page in block 7 Packet X/24 for page in block 8(1) Packet X/27/0 for page in block 8 Packet 8/30/4-15
VPS Data 23
MGD163
(1) If `X24 Position' bit = 0.
Fig.7 Extension packet storage locations.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8.7 Inventory page
SAA5X9X family
If the TXT0.INV ON bit is a logic 1, memory block 8 is used as an inventory page.The inventory page consists of two tables: the Transmitted Page Table (TPT) and the Subtitle Page Table (SPT). In each table, every possible combination of the page tens and units digit, 00H to FFH, is represented by a byte. Each bit of these bytes corresponds to a magazine number so
each page number, from 100 to 8FF, is represented by a bit in the table. The bit for a particular page in the TPT is set when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the `subtitle' page header control bit (C6) set. Before the inventory page is enabled the software must ensure that page request 8 is put on hold.
Bytes in the table
handbook, full pagewidth
column 0
8
16
24
32
39
row n n+1
n+6 n+7
Bytes in each byte
xe0 xe1 xe2 xe3 xe4 xe5 xe6 xe7 xe8 xe9 xea xeb xec xed xee xfef xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xfa xfb xfc xfd xfe xff bit 7 7xx 6xx 5xx 4xx 3xx 2xx 1xx 0 8xx
xc0 xc1 xc2 xc3 xc4 xc5 xc6 xc7 xc8 xc9 xca xcb xcc xcd xce xcf xd0 xd1 xd2 xd3 xd4 xd5 xd6 xd7 xd8 xd9 xda xdb xdc xdd xde xdf
x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x2a x2b x2c x2d x2e x2f x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x3a x3b x3c x3d x3e x3f
x00 x01 x02 x03 x04 x05 x06 x07 x08 x09 x0a x0b x0c x0d x0e x0f x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x1a x1b x1c x1d x1e x1f
MGD160
Fig.8 Table organisation.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
0
handbook, full pagewidth
39
Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0
Transmitted Pages Table
Subtitle Pages Table
Unused Unused Unused Unused Unused Unused Unused Unused Unused 23
MGD165
Fig.9 Inventory page organisation.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8.8 Memory Organisation of SAA5290, SAA5291, SAA5291A and SAA5491
SAA5X9X family
Teletext packets each contain 40 bytes of data and one packet is stored in each row of the text memory, the row used being dependent on the packet number. Packet 0, the page header, is split into 2 parts when it is written into the text memory. The first 8 bytes of the header contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25.
handbook, full pagewidth
Basic Page Block 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Extension Packet Memory Row 0 1 2 Packet X/24(2) Packet X/27/0 Packet 8/30
MGK467
678 OSD only
aw/ag
39 Packet X/0 Packet X/1 Packet X/2 Packet X/3 Packet X/4 Packet X/5 Packet X/6 Packet X/7 Packet X/8 Packet X/9 Packet X/10 Packet X/11 Packet X/12 Packet X/13 Packet X/14 Packet X/15 Packet X/16 Packet X/17 Packet X/18 Packet X/19 Packet X/20 Packet X/21 Packet X/22 Packet X/23 Packet X/24(1)
Control Data 9
VPS Data 23
(1) If X24 Position bit = 1. (2) If X24 Position bit = 0.
Fig.10 Packet storage locations.
1997 Jul 07
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8.9 Packet 26 processing
SAA5X9X family
One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. The family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. This is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default character data overwriting the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten. On the SAA5291,SAA5291A and SAA5491 devices this mechanism is disabled when the Spanish national option is detected as the Spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations corresponding to the characters sent via packet 26 and these will not overwrite the packet 26 characters anyway. The special treatment of Spanish national option is prevented if TXT12.ROM VER R4 is logic 0 or if the TXT8.DISABLE SPANISH is set. Packet 26 data is processed regardless of the TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF disables packet 26 processing. Table 16 VPS data storage
The TXT8.Pkt 26 received bit is set by the hardware whenever a character is written into the page memory by the packet 26 decoding hardware. The flag can be reset by writing a logic 0 into the SFR bit. 8.10 VPS
When the TXT0. VPS ON bit is set, any VPS data present on line 16, field 0 of the CVBS signal at the input of the teletext decoder is error checked and stored in row 25, block 0 for SAA5291, SAA5291A, SAA5491 and row 25, block 9 for SAA5296/7, SAA5296/7A, SAA5496/7 of the basic page memory. The device automatically detects whether teletext or VPS is being transmitted on this line and decodes the data appropriately. Each VPS byte in the memory consists of 4 bi-phase decoded data bits (bits 0 to 3), a bi-phase error flag (bit 4) and three 0s (bits 5 to 7). The TXT13.VPS Received bit is set by the hardware whenever VPS data is acquired. The flag can be reset by writing a logic 0 into the SFR bit. Full details of the VPS system can be found in "Specification of the Domestic Video Programme Delivery Control System (PDC); EBU Tech. 3262-E".
COLUMN ROW 0 TO 9 Row 25 Teletext page header data 10 TO 11 12 TO 13 14 TO 15 16 TO 17 18 TO 19 20 TO 21 22 TO 23 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 VPS byte 15 VPS byte 4 VPS byte 5
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8.11 Wide Screen Signalling (SAA529xA and SAA549x only)
SAA5X9X family
The Wide Screen Signalling data transmitted on line 23 gives information on the aspect ratio and display position of the transmitted picture, the position of subtitles and on the camera/film mode. Some additional bits are reserved for future use. A total of 14 data bits are transmitted. All of the available data bits transmitted by the Wide Screen Signalling signal are captured by the appropriate device in the family and stored in SFRs WSS1, WSS2 and WSS3. The bits are stored as groups of related bits and an error flag is provided for each group to indicate when a transmission error has been detected in one or more of the bits in the group. Wide screen signalling data is only acquired when the TXT8.WSS ON bit is set. The TXT8.WSS RECEIVED bit is set by the hardware whenever wide screen signalling data is acquired. The flag can be reset by writing a logic 0 into the SFR bit. 8.12 525-line world system teletext
The first 8 data bytes of packet X/1/24 are used to extend the Fastext prompt row to 40 characters. These characters are written into whichever part of the memory the packet 24 is being written into (determined by the `X24 Posn' bit). Packets X/0/27/0 contain 5 Fastext page links and the link control byte and are captured, Hamming checked and stored by in the same way as are packets X/27/0 in 625-line text. Packets X/1/27/0 are not captured. Because there are only 2 magazine bits in 525-line text, packets with the magazine bits all set to a logic 0 are referred to as being in magazine 4. Therefore, the broadcast service data packet is packet 4/30, rather than packet 8/30. As in 625 line text, the first 20 bytes of packet 4/30 contain encoded data which is decoded in the same way as that in packet 8/30. The last 12 bytes of the packet contains half of the parity encoded status message. Packet 4/0/30 contains the first half of the message and packet 4/1/30 contains the second half. The last 4 bytes of the message are not written into memory. The first 20 bytes of the each version of the packet are the same so they are stored whenever either version of the packet is acquired. In 525-line text each packet 26 only contains ten 24/18 Hamming encoded data triplets, rather than the 13 found in 625-line text. The tabulation bit is used as an extra bit (the MSB) of the designation code, allowing 32 packet 26s to be transmitted for each page. The last byte of each packet 26 is ignored. The device automatically detects whether 525 or 625-line teletext is being received by checking whether teletext packets are being recognised, and switching to the other system if they aren't. The TXT13.625 TXT bit is set if the device has decided, using the algorithm above, that 625-line text is being received. The TXT13.525 Text bit is set if the device has decided that 525-line text is being received. If the device has not decided which type of text is being received then neither flag is set. The `FORCE ACQ0' and `FORCE ACQ1' bits in TXT17 can be used to override the automatic detection and selection mechanism; see Table 17.
As well as the 625-line teletext format described previously, the family can acquire teletext in the 525-line WST (World System Teletext) format. The 525-line format is similar to the 625-line format but the data rate is lower and there are less data bytes per packet (32 rather than 40). There are still 40 characters per display row so extra packets are sent each of which contains the last 8 characters for four rows. These packets can be identified by looking at the `tabulation bit' (T), which replaces one of the magazine bits in 525-line teletext. When an ordinary packet with T = 1 is received, the decoder puts the data into the four rows starting with that corresponding to the packet number, but with the 2 LSB's set to logic 0. For example, a packet 9 with T = 1 (packet X/1/9) contains data for rows 8, 9, 10 and 11. The error checking carried out on data from packets with T = 1 depends on the setting of the TXT1. 8 BIT bit and the error checking control bits in the page request data and is the same as that applied to the data written into the same memory location in the 625-line format. The rolling time display (the last 8 characters in row 0) is taken from any packets X/1/1, 2 or 3 received. In parallel magazine mode only packets in the correct magazine are used for rolling time. Packet number X/1/0 is ignored. The tabulation bit is also used with extension packets.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
Table 17 Acquisition selection table FORCE ACQ1 0 0 1 1 FORCE ACQ0 0 1 0 1 TIMING automatic 525-line 625-line 625-line
SAA5X9X family
TELETEXT STANDARD automatic 525-line 625-line 525-line
handbook, full pagewidth
0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0
6
7
8 Packet X/0/0 Packet X/0/1 Packet X/0/2 Packet X/0/3 Packet X/0/4 Packet X/0/5 Packet X/0/6 Packet X/0/7 Packet X/0/8 Packet X/0/9 Packet X/0/10 Packet X/0/11 Packet X/0/12 Packet X/0/13 Packet X/0/14 Packet X/0/15 Packet X/0/16 Packet X/0/17 Packet X/0/18 Packet X/0/19 Packet X/0/20 Packet X/0/21 Packet X/0/22 Packet X/0/23 Packet X/0/24(1) Packet X/1/4 Rolling time Packet X/1/1
39
OSD only aw/ag
Packet X/1/8
Packet X/1/12
Packet X/1/16
Packet X/1/20
Packet X/1 /24(1)
MGK468
Control Data 9 23
(1) If X24 Position bit = 1.
Fig.11 Ordinary packet storage locations, 525-line.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
8.13 Fastext detection
SAA5X9X family
When a packet 27, designation code 0 is detected, whether or not it is acquired, the TXT13.FASTEXT bit is set. If the device is receiving 525-line teletext, a packet X/0/27/0 is required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit. When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line transmission, the TXT13.Pkt 8/30 is set. The flag can be reset by writing a logic 0 into the SFR bit. 8.14 Page clearing
This allows the device to be used with teletext transmissions occupying the entire TV channel and with data extracted from different TV broadcast standards (e.g.: MAC packet teletext). 8.16 Independent data services (SAA5291, SAA5291A, SAA5491 only)
When the TXT8.IDS ENABLE bit is set, SAA5291 becomes a receiver for teletext `Independent Data Services'. These services use teletext packet numbers 30 and 31 to transmit data from a central database to a large number of distributed receivers. Unlike normal teletext data, IDS data is not organised into pages but into `data channels'. There are 16 data channels, identified by the magazine number and the LSB of the packet number (actually, the second byte of the magazine and packet number group). Data channel 0 is the familiar packet 8/30, used to transmit broadcast related information. The data channel to be captured by the device is selected by writing to column 0 of the page request RAM. Only IDS packets from the selected data channel are captured and rows 0 to 23 of the basic page memory are used to store the last 24 packets acquired. The first IDS packet acquired after theTXT8.IDS ENABLE bit is set is written into row 0, the next into row 1 and so on until 24 packets have been acquired. The internal packet counter then rolls over and the 25th packet is written into row 0. The hardware never initiates a page clear in IDS mode but if the software initiates one the packet counter is reset to 0 after the memory is cleared. The data bytes in the IDS packers are not error checked in any way. The software must keep track of which of the IDS packets in the memory it has processed and detect newly arrived packets. It can do this by writing a value which cannot be produced by the 8/4 Hamming checker (such as FFH) into column 0 of each row and detecting when it is over written. The 24 packet buffer is sufficient to ensure that the device will not be overwhelmed by IDS data sent in the vertical blanking interval, but it may not be able to cope with full channel IDS data. IDS data is dealt with in the same way for both the 525 and 625-line teletext standards.
When a page header is acquired for the first time after a new page request or a page header is acquired with the erase (C4) bit set the page memory is `cleared' to spaces before the rest of the page arrives. When this occurs, the space code (20H) is written into every location of rows 1 to 23 of the basic page memory, row 1 of the extension packet memory and the row where teletext packet 24 is written. This last row is either row 24 of the basic page memory, if the TXT0.X24 POSN bit is set, or row 0 of the extension packet memory, if the bit is not set. Page clearing takes place before the end of the TV line in which the header arrived which initiated the page clear. This means that the 1 field gap between the page header and the rest of the page which is necessary for many teletext decoders is not required. The software can also initiate a page clear, by setting the TXT9.CLEAR MEMORY bit. When it does so, every location in the memory is cleared. The CLEAR MEMORY bit is not latched so the software does not have to reset it after it has been set. Only one page can be cleared in a TV line so if the software requests a page clear it will be carried out on the next TV line on which the hardware does not force the page to be cleared. A flag, TXT13.PAGE CLEARING, is provided to indicate that a software requested page clear is being carried out. The flag is set when a logic 1 is written into the TXT9.CLEAR MEMORY bit and is reset when the page clear has been completed. At power-on and reset the whole of the page memory is cleared and theTXT13.PAGE CLEARING bit will be set. 8.15 Full channel operation
If the TXT1.FULL FIELD bit is set the device will acquire data transmitted on any TV line, not just during the vertical blanking interval.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
Table 18 Page request RAM for IDS data COL 0 1 to 7 9 9.1 THE DISPLAY Introduction BIT7 X X BIT6 X X BIT5 X X BIT4 X X 9.4 BIT3 Data Ch 3 X BIT2 Data Ch 2 X
SAA5X9X family
BIT1 Data Ch 1 X
BIT0 Data Ch 0 X
National option characters
The capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated on screen displays. The display consists of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the basic page memory. If the TXT7.STATUS ROW TOP bit is set row 24 is displayed at the top of the screen, followed by row 0, but normally memory rows are displayed in numerical order. The teletext memory stores 8 bit character codes which correspond to a number of displayable characters and control characters, which are normally displayed as spaces. The character set of the device is described in more detail below. 9.2 Character matrix
The meanings of some character codes between 20H and 7FH depend on the C12 to C14 language control bits from the teletext page header. The interpretation of the C12 to C14 language control bits is dependent on the East/West bit. 9.5 The twist attribute
In many of the character sets, the `twist' serial attribute (code 1BH) can be used to switch to an alternate basic character code table, e.g. to change from the Hebrew alphabet to the Arabic alphabet on an Arab/Hebrew device. For some national option languages the alternate code table is the default, and a twist control character will switch to the first code table. The display hardware on the devices allows one language to invoke the alternate code table by default when the East/West register bit is a logic 0 and another when the bit is a logic 1. In all of the character sets defined so far, the language which invokes the alternate code table is the same for either setting of the East/West bit. 9.6 On Screen Display symbols
Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed, each pixel is 112 s wide and 1 TV line, in each field, high. 9.3 East/West selection
In common with their predecessors, these devices store teletext pages as a series of 8 bit character codes which are interpreted as either control codes (to change colour, invoke flashing etc.) or displayable characters. When the control characters are excluded, this gives an addressable set of 212 characters at any given time. More characters than this were required to give the language coverage required from the first version of the device, so the TXT4.East/West bit was introduced to allow the meanings of character codes D0H to FFH to be changed, depending on where in Europe the device was to be used. This bit is still used with the other language variants, although the name East/West may not make much sense.
In the character sets character codes 80H to 9FH are OSD symbols not addressed by the teletext decoding hardware. An editor is available to allow these characters to be redefined by the customer. The SAA549x allows another 32 OSD symbols. These are selected using the `graphics' serial attribute. 9.7 Language group identification
The devices have a readable register TXT12 which contains a 5 bit identification code TXT12.ROM VER R4 to TXT12.ROM VER R0 which is intended for use in identifying which character set the device is using.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
9.8 525-line operation
SAA5X9X family
When used with 525-line display syncs, the devices modify their displays such that the bottom line is omitted from each character cell. The character sets have been designed to be readable under these circumstances and anyone designing OSD symbols is advised to consider this mode of operation. 9.9 On Screen Display characters
colour to be changed to any colour with a single control character and independently of the foreground colour. The background colour is changed from the position of the background colour control character. Displayable characters between a `flash' (08H) and a `steady' (09H) control character will flash on and off. Displayable characters between a `conceal display' (18H) character and an alphanumerics or graphics control character are displayed as spaces, unless the TXT7.REVEAL bit is set. The `contiguous graphics' (19H) and `separated graphics' (1AH) characters control the way in which mosaic shapes are displayed. The difference between the two is shown in Fig.12. Control characters encountered between a `hold graphics' (1EH) control character and a `release graphics' (1FH) control character are displayed as the last character displayed in graphics mode, rather than as spaces. From the hold graphics character until the first character displayed in graphics mode the held character is a space. The `start box' (0BH) and `end box' (0AH) characters are used to define teletext boxes. Two start box characters are required to begin a teletext box, with the box starting between the 2 characters. The box ends after an end box character has been encountered. The display can be set up so that different display modes are invoked inside and outside teletext boxes e.g. text inside boxes but TV outside. This is described in Section 9.13. The `normal size' (0CH), `double height' (0DH), `double width' (0EH) and `double size' (0FH) control characters are used to change the size of the characters displayed. If any double height (or double size) characters are displayed on a row the whole of the next row is displayed as spaces. Double height display is not possible on either row 23 or row 24. The character in the position occupied by the right hand half of a double width (or double size) character is ignored, unless it is a control character in which case it takes effect on the next character displayed. This allows double width to be used to produce a display in which blank spaces do not appear when character attributes are changed. The size implying OSD (BCH to BFH) control characters are not standard teletext control characters and have been included in this device to allow OSD messages to be generated with the minimum disruption to the teletext page stored in the memory. These characters are described in full later in this document.
Character codes 80H to 9FH are not addressed by the hardware and can be redefined by the customer, as OSD characters if necessary. The alternative character shapes in columns 8a and 9a (SAA549x only) can be displayed when the `graphics' serial attribute is set. This increases the number of customer definable characters to 64. To ensure compatibility with devices only having 32 OSD characters, the additional OSD characters are only accessible when the TXT4.OSD BANK ENABLE bit is set. If this bit is not set, the characters in columns 8 and 9 will be displayed in both alphanumeric and graphics modes. 9.10 Control characters
Character codes 00H to 1FH, B0H to B7H and BCH to BFH are interpreted as control characters which can be used to change the colour of the characters, the background colour, the size of characters, and various other features. All control characters are normally displayed as spaces. The alphanumerical colour control characters (00H to 07H) are used to change colour of the characters displayed. The graphics control characters (10H to 17H) change the colour of the characters and switch the display into a mode where the codes in columns 2, 3, 6 and 7 of the character table (see the character table above) are displayed as the block mosaic characters in columns 2a, 3a, 6a and 7a. The display of mosaics is switched off using one of the alphanumerics colour control characters. The `new background' character (1DH) the background colour of the display, sets the background colour equal to the current foreground colour. The `black background' character (1CH) changes the background colour to black independently of the current foreground colour. The background colour control characters in the upper half of the code table (B0H to B7H) are additions to the normal teletext control characters which allow the background
1997 Jul 07
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
This is because if two consecutive size implying OSD control characters are used, the first starts the OSD box and the second finishes the OSD box, and therefore no OSD box is defined.
handbook, halfpage
Quadruple width characters must not start in columns 37, 38 or 39 of the display since the whole of the character cannot be displayed. 9.12 Page attributes
mosaics character 7FH contiguous
mosaics character 7FH separated
MGL117
Row 25 of the basic page memory contains control data from the page header of the page stored in the memory. The bits which affect the display are the newsflash (C5), subtitle (C6), suppress header (C7), inhibit display (C10) and language control (C12 to 14) bits. If either the newsflash or the subtitle bit is set a different SFR is used to define the display mode, as described in Section 9.13. The suppress header bit causes the header row (row 0) to be displayed as if every character was a space and the inhibit display bit has this effect on every display row. The language control bits cause certain character codes to be interpreted differently, as described above. 9.13 Display modes
Fig.12 Contiguous and separated mosaics.
9.11
Quadruple width display (SAA549x)
Two successive double width control characters will invoke quadruple width display. Quad width display is terminated by another size control character. Any combination of two of the four controls which invoke double width display (double width, double size, double width OSD and double size OSD) can invoke quad width display. If a double size control character is part of the sequence, characters will be displayed in quad width and double height. To ensure that broadcast teletext pages can be displayed correctly, quadruple width will only be displayed if the TXT4.QUAD WIDTH ENABLE bit is set. If this bit is not set, two successive double width characters will invoke double width display. If quadruple width characters are to be used within OSD boxes (see later section) then the first of the width characters must be either `double width' (OEH) or `double size' (OFH).
The device signals the TVs display circuits to display the R, G and B outputs of the device, rather than the video picture, by outputting a logic 1 on the VDS output. The way in which this signal is switched is controlled by the bits in the TXT5 and TXT6 SFRs. There are 3 control functions text on, background on and picture on. Separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. Also, different SFRs are used depending on whether the newsflash (C5) or subtitle (C6) bits in row 25 of the basic page memory are set (SFR TXT6) or not (SFR TXT5). This allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, TV picture outside) this will be invoked without any further software intervention when such a page is acquired.
1997 Jul 07
41
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
When teletext box control characters are present in the page memory, whichever is relevant of the `Boxes On Row 0', `Boxes On Row 1 to 23' and `Boxes On Row 24' SFR bits in TXT17 must be set if the display mode is to change in the box. These bits are present to allow boxes in certain areas of the screen to be disabled so that teletext boxes can be used for the display of OSD messages without the danger of subtitles in boxes, which may also be in the page memory, being displayed. The use of teletext boxes for OSD messages has been superseded in this device by the OSD box concept, described later, but these bits remain to allow teletext boxes to be used, if required. The COR bits in the TXT5 and TXT6 SFRs control when the COR output of the device is activated (i.e. pulled down). This output is intended to act on the TV's display circuits to reduce the contrast of the video display when it is active. The result of contrast reduction is to improve the readability of the text in a mixed text and video display. The bits in the TXT5 and TXT6 SFRs allow the display to be set up so that, for example, the areas inside teletext boxes will be contrast reduced when a subtitle is being displayed but that the rest of the screen will be displayed as normal video.
SAA5X9X family
Setting the shadow TXT4.SHADOW ENABLE bit will add a `south east' shadow to the text, significantly enhancing its readability in mix mode. Shadowing is illustrated in Fig.13. The readability of text can also be enhanced using `meshing'. Meshing causes the VDS signal to switch so that when the text background colour should be displayed every other pixel is displayed from the video picture. Text foreground pixels are always displayed. The TXT4.BMESH bit enables meshing on areas of the screen within the text display area with black as the background colour. The TXT4.CMESH bit has the same effect on areas with other background colours. Meshing can only be invoked in areas displayed in text mode i.e. where the TXT5.TEXT IN and TXT5.BKGND IN bits are both set to logic 1s, and in OSD boxes. Meshed text can also be shadowed. Meshing is illustrated in Fig.13. The TXT4.TRANS bit causes areas of black background colour to become transparent i.e. video is displayed instead of black background. Black background transparency can also only be invoked in areas displayed in text mode i.e. where the TXT5.TEXT IN and TXT5.BKGND IN bits are both set to a logic 1, and in OSD boxes.
Table 19 Display control bits PICTURE ON 0 0 0 1 1 1 TEXT ON 0 1 1 0 1 1 BACKGROUND ON X 0 1 X 0 1 EFFECT text mode, black screen text mode, background always black text mode TV mode mixed text and TV mode text mode, TV picture outside text area
1997 Jul 07
42
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
normal mix mode handbook, halfpage
,,,, ,,, ,,, ,,, ,,,, ,,, , ,,,, ,, , ,,,, ,,, ,, ,, , ,, ,, ,, , ,,, ,,, ,,, ,,, , ,,, ,, ,,,,, , ,, ,, ,,,, ,,, ,,,,,, ,,,, ,,, ,, , , ,, ,,, ,, ,, , ,,,, ,,, ,, , , ,, ,,, ,, ,,,, ,,, ,, , ,,, ,,, ,,,, ,, , ,, ,,, ,, ,, ,, , , ,, ,
SE shadowing meshing TV picture black text foreground colour
meshing and shadowing
text background colour
MGL118
Fig.13 Meshing and shadowing.
Table 20 Enhanced display mode selection SHADOW 0 0 0 0 0 0 1 1 1 1 1 TRANS 0 0 0 0 1 1 0 0 0 1 1 BMESH 0 0 1 1 X X 0 1 1 X X CMESH 0 1 0 1 0 1 1 0 1 0 1 DISPLAY normal, unshadowed, unmeshed text text with coloured backgrounds meshed, black background solid text with coloured backgrounds solid, black background meshed text with all backgrounds meshed text with coloured backgrounds solid, black background transparent text with coloured backgrounds meshed, black background transparent shadowed text with coloured backgrounds meshed, black background solid shadowed text with coloured backgrounds solid, black background meshed shadowed text with all backgrounds meshed shadowed text with coloured backgrounds solid, black background transparent shadowed text with coloured backgrounds meshed, black background transparent
1997 Jul 07
43
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
9.14 On Screen Display boxes
SAA5X9X family
The size implying OSD control characters (BCH to BFH) are intended to allow OSD messages to be displayed with the minimum disruption to the teletext page stored in the page memory. OSD boxes are not the same as teletext boxes created using the teletext boxing control characters (0AH and 0BH). When one of these characters occurs the display size changes appropriately (to normal size for BCH, double height for BDH, double width for BEH and double size for BFH) and an OSD box starts from the next character position (`set after'). The OSD box ends either at the end of the row of text or at the next size implying OSD character. When an OSD box is ended using another size implying OSD character the box ends at the position of the control character (`set at'). This arrangement allows displays to be created without blank spaces at the ends of the OSD boxes. To prevent control characters from the teletext page affecting the display of the OSD message the flash, teletext box, conceal, separated graphics, twist and hold graphics functions are all reset at the start of an OSD box, as they are at the start of the row. In order to allow the most commonly used display attributes to be set up before the box starts the foreground colour, background colour and mosaics on/off attributes are not reset. The text within an OSD box is always displayed in text mode i.e. as if the Text On and Bkgnd On bits are both set to a logic 1. The type of display produced inside an OSD box is, therefore, dependent on the states of the TXT4.SHADOW ENABLE, TXT4.TRANS ENABLE, TXT4.BMESH ENABLE and TXT4.CMESH ENABLE register bits, as described previously. OSD boxes can only be displayed in TV mode i.e. when the Picture On SFR bit is a logic 1 and the Text On SFR bit is a logic 0, both inside and outside text boxes and for both normal and newsflash/subtitle pages. The display of OSD boxes is not affected by the C7, suppress header, and C10, inhibit display, control bits stored in row 25 of the page memory. 9.15 Screen colour
Screen colour is displayed from 10.5 to 62.5 s after the active edge of the HSync input and on TV lines 23 to 310 inclusive, for a 625-line display, and lines 17 to 260 inclusive for a 525-line display. When the screen colour has been redefined, no TV picture is displayed so the FRAME de-interlace output can be activated, if the SFR bits controlling FRAME are set up to allow this. Table 21 Screen colours SCREEN COL 2 0 0 0 0 1 1 1 1 9.16 SCREEN COL 1 0 0 1 1 0 0 1 1 SCREEN COL 0 0 1 0 1 0 1 0 1 SCREEN COLOUR transparent red green yellow blue magenta cyan white
Redefinable Colours (SAA549x)
The CLUT SFR can be used to load a colour look-up table (CLUT) which allows the 8 foreground colours and 8 background colours to be redefined. Each entry has 6 bits, 2 for each colour component, giving a total palette of 64 colours from which to choose. When the CLUT.CLUT ENABLE bit is a logic 0 the CLUT is disabled and the device will display the normal, full intensity, teletext colours. The meaning of the least significant 6 bits of the CLUT SFR depends on the setting of the CLUT.CLUT ADDRESS bit when the register is written to. If the CLUT.CLUT ADDRESS bit is a logic 1, the 4 LSB's of the SFR contain the address of the entry in the CLUT which will be modified by subsequent writes to the CLUT SFR. If the CLUT.CLUT ADDRESS bit is a logic 0, the 6 LSB's of the SFR define a colour which will be written into the CLUT at the address defined by a previous write to the CLUT SFR. An entry is written into the CLUT whenever the CLUT SFR is written to, unless the CLUT.CLUT ADDRESS bit is set. Table 22 shows which CLUT entry corresponds to which full intensity colour. The contents of the CLUT are not reset at power-up and should be defined by the software before the CLUT is enabled.
The register bits TXT17.SCREEN COL2 to COL0 can be used to define a colour to be displayed in place of TV picture and the black background colour. If the bits are all set to logic 0s, the screen colour is defined as `transparent' and the TV picture and background colour are displayed as normal.
1997 Jul 07
44
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
Table 22 CLUT Address CLUT ADDRESS 0 1 2 3 4 5 6 7 8 9 A B C D E F 9.17 Cursor 9.20 Horizontal timing FULL INTENSITY EQUIVALENT black foreground red foreground green Foreground yellow foreground blue foreground magenta foreground cyan foreground white foreground black background red background green background yellow background blue background magenta background cyan background white background
SAA5X9X family
The Fastext prompt row (packet 24) can be displayed from the extension packet memory by setting the TXT0.DISPLAY X/24 bit. When this bit is set the data displayed on display row 24 is taken from row 0 in the extension packet memory. When the display from extension packet block option is enabled, the display will revert to row 24 of the basic page memory if bit 3 of the link control byte in packet 27 is set. 9.19 Display timing
The display synchronises to the device's HSync and VSync inputs. A typical configuration is shown in Fig.14. The HSync and VSync signals are derived from the signals driving the deflection coils of the TV. The CVBS input is only used to extract teletext from. Locking the display to the signals from the scan circuits allows the device give a stable display under almost all signal conditions. The polarity of the input signals which the device is expecting can be set using the TXT1.H polarity and TXT1.V polarity bits. If the polarity bit is a logic 0, a positive going signal is expected and if it is a logic 1, a negative going signal is expected.
If the TXT7.CURSOR ON bit is set, a cursor is displayed. The cursor operates by reversing the background and foreground colours in the character position pointed to by the active row and column bits in the TXT9 and TXT10 SFRs. Setting the TXT9.CURSOR FREEZE bit, causes the cursor to stay in its current position, no matter what happens to the active row and column positions. This means that the software can read data from the memory (e.g. TOP table information) without affecting the position of the cursor. 9.18 Other display features
Every time an HSync pulse is received the display resynchronizes to its leading edge. To get maximum display stability, the HSync input must have fast edges, free of noise to ensure that there is no uncertainty in the timing of the signal to which the display synchronisation circuits must lock. The display area starts 17.2 s into the line and lasts for 40 s. The display area will be in the centre of the screen if the HSync pulse is aligned with line flyback signal. Therefore, it is better to derive HSync directly from the line flyback or from an output of the line output transformer than from, say, slicing the sandcastle signal as this would introduce delays which would shift the display to the right. 9.21 Vertical timing
Setting the TXT7.DOUBLE HEIGHT bit causes the normal height of all display characters to be doubled and the whole of the display area to be occupied by half of the display rows. Characters normally displayed double height will be displayed quadruple height when this bit is set. Rows 12 to 24 can be enlarged, rather then rows 0 to 11, by setting the TXT7.TOP/BOTTOM bit. This feature can be used for either a user controlled `enlarge' facility or to provide very large characters for OSD. The display of rows 0 to 23 can be disabled by setting the TXT0.DISLAY STATUS ROW ONLY bit. 1997 Jul 07 45
The vertical display timing also resynchronizes to every sync pulse received. This means that the device can produce a stable display on both 625 and 525-line screens. Display starts on the 41st line of each field and continues for 250 lines, or until the end of the field. Normally, television displays are interlaced, i.e. only every other TV line is displayed on each field. It is normal to de-interlace teletext displays to prevent the displayed characters flickering up and down. In many TV designs this
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
is achieved by modulating the vertical deflection current in such a way that odd fields are shifted up and even fields are shifted down on the screen so that lines 1 and 314, 2 and 315 etc. are overlaid. The FRAME output is provided to facilitate this. If the active edge of Vsync occurs in the first half of a TV line this is an even field and the FRAME output should be a logic 0 for this field. Similarly, if VSync is in the second half of the line this is an odd field and FRAME should be a logic1. The algorithm used to derive Frame is such that a consistent output will be obtained no matter where the VSync signal is relative to the HSync signal, even if VSync occurs at the start and mid points of a line. Setting the TXT0.DISABLE FRAME bit forces the FRAME output to a logic 0. Setting the TXT0.AUTO FRAME bit causes the FRAME output to be active when just text is being displayed but to be forced to a logic 0 when any video is being displayed. This allows the de-interlacing function to take place with virtually no software intervention. Some TV architectures do not use the FRAME output but accomplish the de-interlacing function in the vertical deflection IC, under software control, by delaying the start of the scan for one field by half a line, so that lines in this field are moved up by one TV line. In such TVs, VSync may occur in the first half of the line at the start of an odd field and in the second half of the line at the start of an even field. In order to obtain correct de-interlacing in these circumstances, the TXT1.FIELD POLARITY must be set to reverse the assumptions made by the vertical timing circuits on the timing of VSync in each field. The start of the display may be delayed by a line. The `Field Polarity' bit does not affect the FRAME output. 9.22 Display position
SAA5X9X family
The position of the display relative to the HSync and VSync inputs can be varied over a limited range to allow for optimum TV set-up. The horizontal position is controlled by the X0 and X1 bits in TXT16. Table 23 gives the time from the active edge of the HSync to the start of the display area for each setting of X0 and X1. Table 23 Display horizontal position X1 0 0 1 1 X0 0 1 0 1 Hsync TO DISPLAY (s) 17.2 16.2 15.2 14.2
The line on which the display area starts depends on whether the display is 625-line or 525-line and on the setting of the Y0 to Y2 bits in TXT16. Table 24 gives the first display line for each setting of Y0 to Y2, for both 625 and 525-line display. On the other field, the display starts on the equivalent line. Table 24 Display vertical position FIRST LINE FOR DISPLAY Y2 0 0 0 0 1 Y1 0 0 1 1 0 0 1 1 Y0 625-LINE 0 1 0 1 0 1 0 1 42 44 46 48 34 36 38 40 525-LINE 28 30 32 34 20 22 24 26
handbook, halfpage CVBS
VIDEO DECODING SYNC CIRCUITS
RGB CRT DISPLAY
TUNER/IF HSYNC, VSYNC
1 1 1
RGB, VDS
SAA5X9X FRAME
MGK464
Fig.14 Timing configuration.
1997 Jul 07
46
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
handbook, full pagewidth
64 s 23 lines 10.5 s X 52 s Y
40 s
25 rows
TEXT DISPLAY AREA
250 lines
287 lines
312 lines
40 characters TV PICTURE AREA FIELD SCANNING AREA
MGL122
Fig.15 625-line display format.
handbook, full pagewidth
63.55 s 17 lines 10.5 s X 52 s Y
40 s
25 rows
TEXT DISPLAY AREA
225 lines
243 lines
263 lines
40 characters TV PICTURE AREA FIELD SCANNING AREA
MGL123
Fig.16 525-line display format.
1997 Jul 07
47
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
9.23 Clock generator
SAA5X9X family
The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between OSCIN and OSCOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to complete the oscillator circuitry. It is operated in parallel resonance. OSCIN is the high gain amplifier input and OSCOUT is the output. To drive the device externally OSCIN is driven from an external source and OSCOUT is left open-circuit.
handbook, halfpage
OSCGND
handbook, halfpage
OSCGND VSS
C1
(1)
OSCIN external clock
OSCIN
C2 (1) OSCOUT VSS
MLC110 MLC111
not connected
OSCOUT
(1) The values of C1 and C2 depend on the crystal specification: C1 = C2 = 2CL.
Fig.17 Oscillator circuit.
Fig.18 Oscillator circuit driven from external source.
1997 Jul 07
48
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
10 CHARACTER SETS
SAA5X9X family
The two Pan-European character sets are shown in Figs 20 and 21. The character sets for Russian, Greek/Turkish, Arabic/English/French, Thai and Arabic/Hebrew are available on request. 10.1 Pan-European
handbook, full pagewidth
,,,, ,,,, ,,,, ,,,,, ,, ,,,,,, , ,, ,,,,, ,, ,, ,,,,,, ,,,,, ,, ,,, ,,,,, ,, ,,,,, ,,,,,
Fig.19 Pan-European geographical coverage.
MGL133
1997 Jul 07
49
E/W = 0
0 0 0 1 1 0 1 0 0 1 B C D E F D E F 8 9 A 1 1 0 1 1 0 1 6 6a 7 7a 1 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 5 0 0 1 0 0 4 1 0 1 1 0 1 3 3a 1 0 1 1 1 1 1 1 1 1 0 1 1
E/W = 1
b7
0
0
0
SAA5X9X family
Preliminary specification
Fig.20 Pan-European basic character set.
handbook, full pagewidth
1997 Jul 07
nat opt nat opt OSD OSD background black OSD OSD back ground red OSD OSD background green OSD OSD background yellow OSD OSD background blue OSD OSD background magenta OSD OSD background cyan OSD OSD background white
B I T S
b
0
0
0
6 b5
0
0
1
b
4
0
1
0
b 3 b 2 b1 b 0
r o w
column
0
1
2
2a
Philips Semiconductors
0
0
0
0
0
alpha numerics black
graphics black
0
0
0
1
1
alpha numerics red
graphics red
0
0
1
0
2
alpha numerics green
graphics green
0
0
1
1
3
alpha numerics yellow
graphics yellow
nat opt
0
1
0
0
4
alpha numerics blue
graphics blue
nat opt
0
1
0
1
5
alpha numerics magenta
graphics magenta
0
1
1
0
6
alpha numerics cyan
graphics cyan
Economy teletext and TV microcontrollers
50
OSD OSD OSD OSD OSD OSD nat opt nat opt OSD OSD nat opt nat opt OSD OSD normal size OSD nat opt nat opt OSD OSD double height OSD nat opt nat opt OSD OSD double width OSD nat opt OSD OSD double size OSD
0
1
1
1
7
alpha numerics white
graphics white
1
0
0
0
8
flash
conceal display
1
0
0
1
9
steady
contiguous graphics
1
0
1
0
A
end box
separated graphics
1
0
1
1
B
start box
1
1
0
0
C
normal height
black back ground
1
1
0
1
D
double height
new back ground
1
1
1
0
E
double width
hold graphics
1
1
1
1
F
double size
release graphics
MGL124
nat opt
character dependent on the language of page, refer to National Option characters
OSD
customer definable On-Screen Display character
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
handbook, full pagewidth
CHARACTER LANGUAGE E/W C12 C13 C14 ENGLISH(1) 0 0 0 0 23 24 40 5B 5C 5D 5E 5F 60 7B 7C 7D 7E
GERMAN(1)
0
0
0
1
SWEDISH(1)
0
0
1
0
ITALIAN(1)
0
0
1
1
FRENCH(1)
0
1
0
0
SPANISH(1)
0
1
0
1
TURKISH(1)
0
1
1
0
ENGLISH(2)
0
1
1
1
POLISH(1)
1
0
0
0
GERMAN(1)
1
0
0
1
ESTONIAN(1)
1
0
1
0
GERMAN(2)
1
0
1
1
GERMAN(2)
1
1
0
0
SERBO-CROAT(1)
1
1
0
1
CZECH(1)
1
1
1
0
RUMANIAN(1)
1
1
1
1
MGL125
(1) Languages in bold typeface conform to the EBU document SP492 or where superseded ETSI document pr ETS 300 706 with respect to C12/C13/C14 definition. (2) Languages in italic typeface are included for backward compatibility with previous generation of Philips teletext decoders.
Fig.21 National option characters.
1997 Jul 07
51
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
10.2 Russian
SAA5X9X family
handbook, full pagewidth
,,,,,,, ,, , ,,,,,,, ,, ,,,,,,, , ,,,,,,, , ,,,,,,, ,,,,,,, ,,,,,,,,
MGL128
Fig.22 Russian geographical coverage.
10.3
Greek/Turkish
handbook, full pagewidth
, ,, ,,,,, , ,,, ,,,,, ,, ,,, ,,,,,, ,,, ,,,,, ,,,,,
Fig.23 Greek/Turkish geographical coverage. 1997 Jul 07 52
MGL129
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
10.4 Arabic/English/French
SAA5X9X family
handbook, full pagewidth
,, ,,,,,,,,, ,, , ,,,,,,,,, , ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,,
Fig.24 Arabic/English/French geographical coverage.
MGL131
10.5
Thai
handbook, full pagewidth
,, ,, ,,,,,,, ,,,,, ,,,,, ,,,,,, ,,, ,
Fig.25 Thai geographical coverage. 53
MGL132
1997 Jul 07
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
10.6 Arabic/Hebrew
SAA5X9X family
book, full pagewidth
,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,,
MGL130
Fig.26 Arabic/Hebrew geographical coverage.
1997 Jul 07
54
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI VO IO IIOK Tamb Tstg Note 1. This value has an absolute maximum of 6.5 V independent of VDD. 12 CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDD IDDM VDD IDDM IDDA IDDT supply voltage (VDD to VSS) microcontroller supply current supply voltage microcontroller supply current analog supply current teletext supply current SAA5290, SAA5291, SAA5291A, SAA5491 teletext supply current SAA5296/7, SAA5296/7A, SAA5496/7 4.5 - 4.5 - - - 5.0 25 5.0 20 35 40 PARAMETER CONDITIONS MIN. PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current operating ambient temperature storage temperature note 1 note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 - - -20 -55
SAA5X9X family
MAX. +6.5 VDD + 0.5 VDD + 0.5 10 20 +70 +125 V V V
UNIT
mA mA C C
TYP.
MAX.
UNIT
5.5 40 5.5 35 50 65
V mA V mA mA mA
IDDT
-
50
80
mA
Digital inputs RESET, EA VIL VIH ILI CI Vthf Vthr VHYS CI LOW-level input voltage HIGH-level input voltage input leakage current input capacitance VI = 0 to VDD -0.3 0.7VDD -10 - 0.2VDD - - - - - - - - - - 0.2VDD - 0.1 VDD + 0.3 +10 4 - 0.8VDD 4 V V A pF
HSYNC AND VSYNC switching threshold falling switching threshold rising hysteresis voltage input capacitance V V V pF
0.33VDD -
1997 Jul 07
55
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
SYMBOL Digital outputs R, G AND B; VOL VOH ZO CL IO tr tf VDS VOL VOH CL tr tf
NOTE
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1 IOL = 2 mA IOH = -2 mA 0 - - - between 10 and 90%; CL = 50 pF between 90 and 10%; CL = 50 pF IOL = 1.6 mA IOH = -1.6 mA between 10 and 90%; CL = 50 pF between 90 and 10%; CL = 50 pF - - - - - - - - 0.2 150 50 -4 20 20 V pF mA ns ns VRGBREF - 0.3 VRGBREF VRGBREF + 0.4 V
LOW-level output voltage HIGH-level output voltage output impedance load capacitance DC output current output rise time output fall time
LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time
0 VDD - 0.3 - - -
- - - - -
0.2 VDD + 0.4 50 20 20
V V pF ns ns
R, G, B AND VDS tskew skew delay between any two pins - - 20 ns
COR (OPEN-DRAIN OUTPUT) VOH VOL IOL CL VOH VOL IOL CL HIGH-level pull-up output voltage LOW-level output voltage LOW-level output current load capacitance IOL = 2 mA - 0 - - IOL = 8 mA IOL = -8 mA 0 VDD - 0.5 -8 - - - - - - - - - VDD 0.5 2 25 V V mA pF
FRAME, RD, WR, ALE, PSEN, AD0 TO AD7, A8 TO A15 HIGH-level output voltage LOW-level output voltage LOW-level output current load capacitance 0.5 VDD +8 100 V V mA pF
1997 Jul 07
56
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.4 VIL VIH CI VOL CL VIL VIH CI VOL CL VIL VIH CI VOL CL tf LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage load capacitance IOL = 3.2 mA -0.3 0.2VDD + 0.9 - 0 - -0.3 0.2VDD + 0.9 - IOL = 10 mA 0 - -0.3 3.0 - IOL = 3 mA between 3 and 1 V 0 - - - - - - - - - - - - - - - - - - 0.2VDD - 0.1 VDD + 0.3 4 0.45 50 0.2VDD - 0.1 VDD + 0.3 4 0.45 50 V V pF V pF
P0.5 AND P0.6 LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage load capacitance V V pF V pF
P1.6 AND P1.7 LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage load capacitance output fall time +1.5 VDD + 0.3 5 0.5 400 200 V V pF V pF ns
Analog inputs CVBS0 AND CVBS1 Vsync Vvid(p-p) Zsource VIH ZI CI IREF Rgnd VI II resistor to ground - -0.3 - 27 - - - VDD 12 k sync voltage amplitude video input voltage amplitude (peak-to-peak value) source impedance HIGH level input voltage input impedance input capacitance 0.1 0.7 - 3.0 2.5 - 0.3 1.0 - - 5.0 - 0.6 1.4 250 VDD + 0.3 - 10 V V V k pF
RGBREF; NOTE 1 input voltage DC input current V mA
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
SYMBOL REF+, REF- VIH ZI CI VIL
PARAMETER
CONDITIONS
MIN. -
TYP.
MAX.
UNIT
HIGH level input voltage input impedance input capacitance LOW-level input voltage
3.0 2.5 - -0.3
VDD + 0.3 - 10 VDD
V k pF V
5.0 - -
ADC0, ADC1 and ADC2 Analog input/output BLACK CBLACK VBLACK ILI storage capacitor to ground black level voltage for nominal sync amplitude input leakage current - 1.8 -10 100 2.15 - - 2.5 +10 nF V A
Crystal oscillator OSCIN VIL VIH CI OSCOUT CO fxtal CL C1 C0 Rr Txtal Xj Xd Notes 1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF and the R, G and B pins is 150 . 2. Crystal order number 4322 143 05561. output capacitance - - - Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C - - - -20 - - - 12 32 18.5 4.9 35 +25 - - 10 - - - - - +70 50 x 10-6 30 x 10-6 pF LOW-level input voltage HIGH-level input voltage input capacitance -0.3 0.7VDD - - - - 0.2VDD - 0.1 VDD + 0.3 10 V V pF
CRYSTAL SPECIFICATION; NOTE 2 nominal frequency load capacitance series capacitance parallel capacitance resonance resistance temperature range adjustment tolerance drift MHz pF fF pF C
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
13 CHARACTERISTICS FOR THE I2C-BUS INTERFACE SYMBOL SCL timing tHD;STA tLOW tHIGH trC tfC SDA timing tSU;DAT1 tHD;DAT tSU;STA tSU;STO tBUF trD tfD Notes data set-up time data hold time repeated START set-up time STOP condition set-up time bus free time SDA rise time SDA fall time 250 ns 0 ns 4.7 s 4.0 s 4.7 s 1.0 s 0.3 s note 1 note 1 note 1 note 1 note 1 note 3 0.3 s; note 4 START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time 4.0 s 4.7 s 4.0 s 1.0 s 0.3 s note 1 note 1 4.0 s; note 2 note 3 0.3 s; note 4 PARAMETER INPUT OUTPUT
SAA5X9X family
I2C-BUS SPECIFICATION 4.0 s 4.7 s 4.0 s 1.0 s 0.3 s 250 ns 0 ns 4.7 s 4.0 s 4.7 s 1.0 s 0.3 s
1. This parameter is determined by the user software. It must comply with the I2C-bus specification. 2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency. Alternatively, the SCL pulse must be timed by software. 3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 s. 4. The maximum capacitance on bus lines SDA and SCL is 400 pF.
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handbook, full pagewidth
1997 Jul 07
repeated START condition START condition STOP condition t rD t SU;STA 0.7V DD 0.3VDD t fC t BUF t SU;STO 0.7VDD 0.3VDD t SU;DAT3 t SU;DAT2
MLC104
Philips Semiconductors
START or repeated START condition
SDA (input / output)
Economy teletext and TV microcontrollers
60
t HIGH t SU;DAT1 t HD;DAT
t fD
t rC
SCL (input / output)
t HD;STA
t LOW
SAA5X9X family
Preliminary specification
Fig.27 I2C-bus interface timing.
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
14 QUALITY SPECIFICATIONS
SAA5X9X family
This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E"; "Quality Reference Handbook, order number 9398 510 63011". The principal requirements are shown in Table 25 to 28. Table 25 Acceptance tests per lot; note 1 TEST Mechanical Electrical cumulative target: <80 ppm cumulative target: <80 ppm REQUIREMENTS
Table 26 Processability tests (by package family); note 2 TEST solderability mechanical <7% LTPD <15% LTPD REQUIREMENTS
solder heat resistance <15% LTPD Table 27 Reliability tests (by process family); note 3 TEST operational life humidity life temperature cycling performance 168 hours at Tj = 150 C temperature, humidity, bias 1000 hours, 85 C, 85% RH (or equivalent test) Tstg(min) to Tstg(max) CONDITIONS REQUIREMENTS <1000 FPM at Tj = 70 C <2000 FPM <2000 FPM
Table 28 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS ESD Human body model 100 pF, 1.5 k ESD Machine model 200 pF, 0 latch-up Notes to Tables 25, 26 and 27 1. ppm = fraction of defective devices, in parts per million. 2. LTPD = Lot Tolerance Percent Defective. 3. FPM = fraction of devices failing at test condition, in failures per million. 2000 V 200 V 100 mA, 1.5 x VDD (absolute maximum) REQUIREMENTS
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40 V A0 RC SCL SDA VDD VDD A1
VDD
VDD
ndbook, full pagewidth
1997 Jul 07
VDD 47 F 100 nF VSS VSS VSS P2.0/TPWM 1 52 51 50 49 48 47 46 45 44 43 42 41 40 OSCGND VDDT VDDA VSYNC HSYNC VDS R G B RGBREF 31 30 29 28 27 P3.4/PWM7 COR VSSD FRAME 26 VSS
MGK463
Vtune VDD VSS A2
PH2369
EEPROM PCF8582E
VSS VSS
Philips Semiconductors
VDD P1.5 P1.4 P1.7/SDA P1.6/SCL P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDM RESET XTALOUT XTALIN 22 pF VDD 47 F 12MHz VDD 100 nF VSS field flyback line flyback 2.2 F VDD VDD IR RECEIVER TV control signals
brightness 2 3 4 5 6 7 8 9 10 11 12 13 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 VSS P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSD VSS P0.0 14 39 38 37 36 35 34 33 32 15 16 17 18 19 20 21 22 23 24 25 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 1 k VSSA VSS CVBS0 CVBS1 BLACK IREF 100 nF VSS 27 k 100 nF CVBS (IF) 100 nF
P2.1/PWM0
contrast
15 APPLICATION INFORMATION
saturation
hue
volume (L)
volume (R)
Vafc
VDD
Economy teletext and TV microcontrollers
62
SAA5X9X
VSS
VSS
VDD
VDD
to TV's display circuits
CVBS (SCART)
SAA5X9X family
Preliminary specification
Fig.28 Application diagram.
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
16 EMC GUIDELINES If possible, a ground plane under the whole IC should be present, i.e. no signal tracks running underneath the IC as shown in Fig.29. The ground plane under the IC should be connected by the widest possible connection back to the ground connection of the PCB, and electrolytic decoupling capacitor. It should preferably not connect to other grounds on the way and no wire links should be present in this connection. The use of wire links increases ground bounce by introducing inductance into the ground, thereby reducing the electrolytic capacitor's decoupling efficiency. The supply pins should be decoupled at the pin, to the ground plane under the IC. This is easily accomplished
SAA5X9X family
when using SM capacitors (which are also most effective at high frequencies). Each supply pin should be connected separately to the power connection of the PCB, preferably via at least one wire link which: 1. May be replaced by a ferrite or inductor at a later point if necessary 2. Will introduce a small amount of inductance. Signals connected to the +5 V supply e.g. via a pull-up resistors, should be connected to the +5 V supply before the wire link to the IC (i.e. not the IC side). This will prevent if from being polluted and conduct or radiate noise onto signal lines, which may then radiate themselves. OSCGND should connect only to the crystal load capacitors (and not GND).
handbook, full pagewidth
GND +5 V
electrolytic decoupling capacitor (2 F)
wire links other GND connections SM decoupling capacitors (10 to 100 nF) VDDM VDDD VDDA
under-IC GND plane GND connection note: no wire links
under-IC GND plane
VSSD
IC VSSA
MGL127
Fig.29 Power supply and GND connections for SOT247-1.
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
17 PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SAA5X9X family
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5X9X family
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA A A2 A1
Q (A 3) Lp L detail X
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-12-15 95-02-04
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
18 SOLDERING 18.1 Introduction
SAA5X9X family
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 18.2 18.2.1 SDIP SOLDERING BY DIPPING OR BY WAVE
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. 18.3.2 WAVE SOLDERING
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 18.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 18.3 18.3.1 QFP REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1997 Jul 07 66
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5X9X family
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/00/01/pp68
Date of release: 1997 Jul 07
Document order number:
9397 750 01952

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